1 2/* 3Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 4 5Permission is hereby granted, free of charge, to any person obtaining a copy of 6this software and associated documentation files (the "Software"), to deal in 7the Software without restriction, including without limitation the rights to 8use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 9of the Software, and to permit persons to whom the Software is furnished to do 10so, subject to the following conditions: 11 12The above copyright notice and this permission notice shall be included in all 13copies or substantial portions of the Software. 14 15THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 17NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 20WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22Except as contained in this notice, the name of the XFree86 Project shall not 23be used in advertising or otherwise to promote the sale, use or other dealings 24in this Software without prior written authorization from the XFree86 Project. 25*/ 26 27/* 28 * regs3v.h 29 * 30 * Port to 4.0 design level 31 * 32 * S3 ViRGE driver 33 * 34 * Portions based on code containing the following notices: 35 ********************************************************** 36 * 37 * Written by Jake Richter Copyright (c) 1989, 1990 Panacea Inc., Londonderry, 38 * NH - All Rights Reserved 39 * 40 * This code may be freely incorporated in any program without royalty, as long 41 * as the copyright notice stays intact. 42 * 43 * Additions by Kevin E. Martin (martin@cs.unc.edu) 44 * 45 * KEVIN E. MARTIN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 46 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 47 * EVENT SHALL KEVIN E. MARTIN BE LIABLE FOR ANY SPECIAL, INDIRECT OR 48 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF 49 * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 50 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 51 * PERFORMANCE OF THIS SOFTWARE. 52 * 53 */ 54 55/* Taken from accel/s3_virge code */ 56/* 23/03/97 S. Marineau: fixed bug with first Doubleword Offset macros 57 * and added macro CommandWaitIdle to wait for the command FIFO to empty 58 */ 59 60 61#ifndef _REGS3V_H 62#define _REGS3V_H 63 64#define S3_ViRGE_SERIES(chip) ((chip&0xfff0)==0x31e0) 65#define S3_ViRGE_GX2_SERIES(chip) (chip == S3_ViRGE_GX2 || chip == S3_TRIO_3D_2X) 66#define S3_ViRGE_MX_SERIES(chip) (chip == S3_ViRGE_MX || chip == S3_ViRGE_MXP) 67#define S3_ViRGE_MXP_SERIES(chip) (chip == S3_ViRGE_MXP) 68#define S3_ViRGE_VX_SERIES(chip) ((chip&0xfff0)==0x3de0) 69#define S3_TRIO_3D_SERIES(chip) (chip == S3_TRIO_3D) 70#define S3_TRIO_3D_2X_SERIES(chip) (chip == S3_TRIO_3D_2X) 71 72/* Chip tags */ 73#define PCI_S3_VENDOR_ID PCI_VENDOR_S3 74#define S3_UNKNOWN 0 75#define S3_ViRGE PCI_CHIP_VIRGE 76#define S3_ViRGE_VX PCI_CHIP_VIRGE_VX 77#define S3_ViRGE_DXGX PCI_CHIP_VIRGE_DXGX 78#define S3_ViRGE_GX2 PCI_CHIP_VIRGE_GX2 79#define S3_ViRGE_MX PCI_CHIP_VIRGE_MX 80#define S3_ViRGE_MXP PCI_CHIP_VIRGE_MXP 81#define S3_TRIO_3D PCI_CHIP_Trio3D 82#define S3_TRIO_3D_2X PCI_CHIP_Trio3D_2X 83 84/* Subsystem Control Register */ 85#define GPCTRL_NC 0x0000 86#define GPCTRL_ENAB 0x4000 87#define GPCTRL_RESET 0x8000 88 89 90/* Command Register */ 91#define CMD_OP_MSK (0xf << 27) 92#define CMD_BITBLT (0x0 << 27) 93#define CMD_RECT ((0x2 << 27) | 0x0100) 94#define CMD_LINE (0x3 << 27) 95#define CMD_POLYFILL (0x5 << 27) 96#define CMD_NOP (0xf << 27) 97 98#define BYTSEQ 0 99#define _16BIT 0 100#define PCDATA 0x80 101#define INC_Y CMD_YP 102#define YMAJAXIS 0 103#define INC_X CMD_XP 104#define DRAW 0x0020 105#define LINETYPE 0x0008 106#define LASTPIX 0 107#define PLANAR 0 /* MIX_MONO_SRC */ 108#define WRTDATA 0 109 110/* 111 * Short Stroke Vector Transfer Register (The angular Defs also apply to the 112 * Command Register 113 */ 114#define VECDIR_000 0x0000 115#define VECDIR_045 0x0020 116#define VECDIR_090 0x0040 117#define VECDIR_135 0x0060 118#define VECDIR_180 0x0080 119#define VECDIR_225 0x00a0 120#define VECDIR_270 0x00c0 121#define VECDIR_315 0x00e0 122#define SSVDRAW 0x0010 123 124/* Command AutoExecute */ 125#define CMD_AUTOEXEC 0x01 126 127/* Command Hardware Clipping Enable */ 128#define CMD_HWCLIP 0x02 129 130/* Destination Color Format */ 131#define DST_8BPP 0x00 132#define DST_16BPP 0x04 133#define DST_24BPP 0x08 134 135/* BLT Mix modes */ 136#define MIX_BITBLT 0x0000 137#define MIX_MONO_SRC 0x0040 138#define MIX_CPUDATA 0x0080 139#define MIX_MONO_PATT 0x0100 140#define MIX_COLOR_PATT 0x0000 141#define MIX_MONO_TRANSP 0x0200 142 143/* Image Transfer Alignments */ 144#define CMD_ITA_BYTE 0x0000 145#define CMD_ITA_WORD 0x0400 146#define CMD_ITA_DWORD 0x0800 147 148/* First Doubleword Offset (Image Transfer) */ 149#define CMD_FDO_BYTE0 0x00000 150#define CMD_FDO_BYTE1 0x01000 151#define CMD_FDO_BYTE2 0x02000 152#define CMD_FDO_BYTE3 0x03000 153 154/* X Positive, Y Positive (Bit BLT) */ 155#define CMD_XP 0x2000000 156#define CMD_YP 0x4000000 157 158/* 2D or 3D Select */ 159#define CMD_2D 0x00000000 160#define CMD_3D 0x80000000 161 162/* The Mix ROPs (selected ones, not all 256) */ 163#if 0 164 165#define ROP_0 (0x00<<17) 166#define ROP_DSon (0x11<<17) 167#define ROP_DSna (0x22<<17) 168#define ROP_Sn (0x33<<17) 169#define ROP_SDna (0x44<<17) 170#define ROP_Dn (0x55<<17) 171#define ROP_DSx (0x66<<17) 172#define ROP_DSan (0x77<<17) 173#define ROP_DSa (0x88<<17) 174#define ROP_DSxn (0x99<<17) 175#define ROP_D (0xaa<<17) 176#define ROP_DSno (0xbb<<17) 177#define ROP_S (0xcc<<17) 178#define ROP_SDno (0xdd<<17) 179#define ROP_DSo (0xee<<17) 180#define ROP_1 (0xff<<17) 181 182/* ROP -> (ROP & P) | (D & ~P) */ 183#define ROP_0_PaDPnao /* DPna */ (0x0a<<17) 184#define ROP_DSon_PaDPnao /* PDSPaox */ (0x1a<<17) 185#define ROP_DSna_PaDPnao /* DPSana */ (0x2a<<17) 186#define ROP_Sn_PaDPnao /* SPDSxox */ (0x3a<<17) 187#define ROP_SDna_PaDPnao /* DPSDoax */ (0x4a<<17) 188#define ROP_Dn_PaDPnao /* DPx */ (0x5a<<17) 189#define ROP_DSx_PaDPnao /* DPSax */ (0x6a<<17) 190#define ROP_DSan_PaDPnao /* DPSDnoax */ (0x7a<<17) 191#define ROP_DSa_PaDPnao /* DSPnoa */ (0x8a<<17) 192#define ROP_DSxn_PaDPnao /* DPSnax */ (0x9a<<17) 193#define ROP_D_PaDPnao /* D */ (0xaa<<17) 194#define ROP_DSno_PaDPnao /* DPSnao */ (0xba<<17) 195#define ROP_S_PaDPnao /* DPSDxax */ (0xca<<17) 196#define ROP_SDno_PaDPnao /* DPSDanax */ (0xda<<17) 197#define ROP_DSo_PaDPnao /* DPSao */ (0xea<<17) 198#define ROP_1_PaDPnao /* DPo */ (0xfa<<17) 199 200 201/* S -> P */ 202#define ROP_DPon (0x05<<17) 203#define ROP_DPna (0x0a<<17) 204#define ROP_Pn (0x0f<<17) 205#define ROP_PDna (0x50<<17) 206#define ROP_DPx (0x5a<<17) 207#define ROP_DPan (0x5f<<17) 208#define ROP_DPa (0xa0<<17) 209#define ROP_DPxn (0xa5<<17) 210#define ROP_DPno (0xaf<<17) 211#define ROP_P (0xf0<<17) 212#define ROP_PDno (0xf5<<17) 213#define ROP_DPo (0xfa<<17) 214 215/* ROP -> (ROP & S) | (~ROP & D) */ 216#define ROP_DPSDxax (0xca<<17) 217#define ROP_DSPnoa (0x8a<<17) 218#define ROP_DPSao (0xea<<17) 219#define ROP_DPSoa (0xa8<<17) 220#define ROP_DSa (0x88<<17) 221#define ROP_SSPxDSxax (0xe8<<17) 222#define ROP_SDPoa (0xc8<<17) 223#define ROP_DSPnao (0xae<<17) 224#define ROP_SSDxPDxax (0x8e<<17) 225#define ROP_DSo (0xee<<17) 226#define ROP_SDPnao (0xce<<17) 227#define ROP_SPDSxax (0xac<<17) 228#define ROP_SDPnoa (0x8c<<17) 229#define ROP_SDPao (0xec<<17) 230 231/* ROP_sp -> (ROP_sp & S) | (D & ~S) */ 232#define ROP_0_SaDSnao /* DSna */ (0x22<<17) 233#define ROP_DPa_SaDSnao /* DPSnoa */ (0xa2<<17) 234#define ROP_PDna_SaDSnao /* DSPDoax */ (0x62<<17) 235#define ROP_P_SaDSnao /* DSPDxax */ (0xe2<<17) 236#define ROP_DPna_SaDSnao /* DPSana */ (0x2a<<17) 237#define ROP_D_SaDSnao /* D */ (0xaa<<17) 238#define ROP_DPx_SaDSnao /* DPSax */ (0x6a<<17) 239#define ROP_DPo_SaDSnao /* DPSao */ (0xea<<17) 240#define ROP_DPon_SaDSnao /* SDPSaox */ (0x26<<17) 241#define ROP_DPxn_SaDSnao /* DSPnax */ (0xa6<<17) 242#define ROP_Dn_SaDSnao /* DSx */ (0x66<<17) 243#define ROP_PDno_SaDSnao /* SDPSanax */ (0xe6<<17) 244#define ROP_Pn_SaDSnao /* PSDPxox */ (0x2e<<17) 245#define ROP_DPno_SaDSnao /* DSPnao */ (0xae<<17) 246#define ROP_DPan_SaDSnao /* SDPSnoax */ (0x6e<<17) 247#define ROP_1_SaDSnao /* DSo */ (0xee<<17) 248 249#endif 250 251 252#define MAXLOOP 0x0fffff /* timeout value for engine waits, 0.5 secs */ 253 254/* Wait until "v" queue entries are free */ 255#define WaitQueue(v) \ 256 if (ps3v->NoPCIRetry) { \ 257 do { int loop=0; mem_barrier(); \ 258 while ((((IN_SUBSYS_STAT()) & 0x1f00) < (((v)+2) << 8)) && (loop++<MAXLOOP)); \ 259 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 260 } while (0); } 261 262/* Wait until GP is idle and queue is empty */ 263#define WaitIdleEmpty() \ 264 do { int loop=0; mem_barrier(); \ 265 if(S3_TRIO_3D_SERIES(ps3v->Chipset)) \ 266 while (((IN_SUBSYS_STAT() & 0x3f802000 & 0x20002000) != 0x20002000) && \ 267 (loop++<MAXLOOP)); \ 268 else \ 269 while (((IN_SUBSYS_STAT() & 0x3f00) != 0x3000) && (loop++<MAXLOOP)); \ 270 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 271 } while (0) 272 273/* Wait until GP is idle */ 274#define WaitIdle() \ 275 do { int loop=0; mem_barrier(); \ 276 while ((!(IN_SUBSYS_STAT() & 0x2000)) && (loop++<MAXLOOP)); \ 277 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 278 } while (0) 279 280 281/* Wait until Command FIFO is empty */ 282#define WaitCommandEmpty() do { int loop=0; mem_barrier(); \ 283 if (S3_ViRGE_GX2_SERIES(S3_ViRGE_GX2) || S3_ViRGE_MX_SERIES(ps3v->Chipset)) \ 284 while ((!(((((mmtr)s3vMmioMem)->subsys_regs.regs.adv_func_cntl)) & 0x400)) && (loop++<MAXLOOP)); \ 285 else if (S3_TRIO_3D_SERIES(ps3v->Chipset)) \ 286 while (((IN_SUBSYS_STAT() & 0x5f00) != 0x5f00) && (loop++<MAXLOOP)); \ 287 else \ 288 while ((!(((((mmtr)s3vMmioMem)->subsys_regs.regs.adv_func_cntl)) & 0x200)) && (loop++<MAXLOOP)); \ 289 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 290 } while (0) 291 292/* Wait until a DMA transfer is done */ 293#define WaitDMAEmpty() \ 294 do { int loop=0; mem_barrier(); \ 295 while (((((mmtr)s3vMmioMem)->dma_regs.regs.cmd.write_pointer) != (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.read_pointer)) && (loop++<MAXLOOP)); \ 296 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 297 } while(0) 298 299 300 301 302 303#define RGB8_PSEUDO (-1) 304#define RGB16_565 0 305#define RGB16_555 1 306#define RGB32_888 2 307 308#endif /* _REGS3V_H */ 309 310