1 2/* 3Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 4 5Permission is hereby granted, free of charge, to any person obtaining a copy of 6this software and associated documentation files (the "Software"), to deal in 7the Software without restriction, including without limitation the rights to 8use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 9of the Software, and to permit persons to whom the Software is furnished to do 10so, subject to the following conditions: 11 12The above copyright notice and this permission notice shall be included in all 13copies or substantial portions of the Software. 14 15THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 17NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 20WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22Except as contained in this notice, the name of the XFree86 Project shall not 23be used in advertising or otherwise to promote the sale, use or other dealings 24in this Software without prior written authorization from the XFree86 Project. 25*/ 26 27#ifndef _S3V_MACROS_H 28#define _S3V_MACROS_H 29 30/* use these macros and INREG/OUTREG to access the extended registers 31 of s3 virge -- add any others you need here */ 32 33/* miscellaneous registers */ 34#define SUBSYS_STAT_REG 0x8504 35#define ADV_FUNC_CNTR 0x850c 36 37/* memory port controller registers */ 38#define FIFO_CONTROL_REG 0x8200 39#define MIU_CONTROL_REG 0x8204 40#define STREAMS_TIMEOUT_REG 0x8208 41#define MISC_TIMEOUT_REG 0x820c 42 43/* Cursor Registers */ 44#define HWCURSOR_MODE_CR45 0x45 45#define HWCURSOR_ADDR_LOW_CR4D 0x4d 46#define HWCURSOR_ADDR_HIGH_CR4C 0x4c 47 48/* streams registers */ 49#define PSTREAM_CONTROL_REG 0x8180 50#define COL_CHROMA_KEY_CONTROL_REG 0x8184 51#define SSTREAM_CONTROL_REG 0x8190 52#define CHROMA_KEY_UPPER_BOUND_REG 0x8194 53#define SSTREAM_STRETCH_REG 0x8198 54#define BLEND_CONTROL_REG 0x81A0 55#define PSTREAM_FBADDR0_REG 0x81C0 56#define PSTREAM_FBADDR1_REG 0x81C4 57#define PSTREAM_STRIDE_REG 0x81C8 58#define DOUBLE_BUFFER_REG 0x81CC 59#define SSTREAM_FBADDR0_REG 0x81D0 60#define SSTREAM_FBADDR1_REG 0x81D4 61#define SSTREAM_STRIDE_REG 0x81D8 62#define OPAQUE_OVERLAY_CONTROL_REG 0x81DC 63#define K1_VSCALE_REG 0x81E0 64#define K2_VSCALE_REG 0x81E4 65#define DDA_VERT_REG 0x81E8 66#define STREAMS_FIFO_REG 0x81EC 67#define PSTREAM_START_REG 0x81F0 68#define PSTREAM_WINDOW_SIZE_REG 0x81F4 69#define SSTREAM_START_REG 0x81F8 70#define SSTREAM_WINDOW_SIZE_REG 0x81FC 71 72/* image write stuff */ 73#define SRC_BASE 0xA4D4 74#define DEST_BASE 0xA4D8 75#define CLIP_L_R 0xA4DC 76#define CLIP_T_B 0xA4E0 77#define DEST_SRC_STR 0xA4E4 78#define MONO_PAT_0 0xA4E8 79#define MONO_PAT_1 0xA4EC 80#define PAT_BG_CLR 0xA4F0 81#define PAT_FG_CLR 0xA4F4 82#define SRC_BG_CLR 0xA4F8 83#define SRC_FG_CLR 0xA4FC 84#define CMD_SET 0xA500 85#define RWIDTH_HEIGHT 0xA504 86#define RSRC_XY 0xA508 87#define RDEST_XY 0xA50C 88 89/* Local Periperal Bus Registers */ 90 91#define DDC_REG 0xFF20 92#define BLT_BUG 0x00000001 93#define MONO_TRANS_BUG 0x00000002 94 95 96#define MAXLOOP 0x0fffff /* timeout value for engine waits, 0.5 secs */ 97 98/* Switchable per chipset, must be initialized prior to a mode */ 99/* switch! */ 100#define WAITFIFO(n) ((*ps3v->pWaitFifo)(ps3v,n)) 101#define WAITCMD() ((*ps3v->pWaitCmd)(ps3v)) 102 103#define WAITIDLE()\ 104 do { int loop=0; mem_barrier(); \ 105 while(((INREG(SUBSYS_STAT_REG) & 0x3f00) < 0x3000) && (loop++<MAXLOOP)) \ 106 if (loop >= MAXLOOP) S3VGEReset(pScrn,1,__LINE__,__FILE__); \ 107 } while (0) 108 109#define CHECK_DEST_BASE(y,h)\ 110 if((y < ps3v->DestBaseY) || ((y + h) > (ps3v->DestBaseY + 2048))) {\ 111 ps3v->DestBaseY = ((y + h) <= 2048) ? 0 : y;\ 112 WAITFIFO(1);\ 113 OUTREG(DEST_BASE, ps3v->DestBaseY * ps3v->Stride);\ 114 }\ 115 y -= ps3v->DestBaseY 116 117#define CHECK_SRC_BASE(y,h)\ 118 if((y < ps3v->SrcBaseY) || ((y + h) > (ps3v->SrcBaseY + 2048))) {\ 119 ps3v->SrcBaseY = ((y + h) <= 2048) ? 0 : y;\ 120 WAITFIFO(1);\ 121 OUTREG(SRC_BASE, ps3v->SrcBaseY * ps3v->Stride);\ 122 }\ 123 y -= ps3v->SrcBaseY 124 125 126#endif /* _S3V_MACROS_H */ 127