1/* Header: //Mercury/Projects/archives/XFree86/4.0/regsmi.h-arc 1.11 14 Sep 2000 11:17:30 Frido $ */ 2 3/* 4Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 5Copyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. 6 7Permission is hereby granted, free of charge, to any person obtaining a copy of 8this software and associated documentation files (the "Software"), to deal in 9the Software without restriction, including without limitation the rights to 10use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 11of the Software, and to permit persons to whom the Software is furnished to do 12so, subject to the following conditions: 13 14The above copyright notice and this permission notice shall be included in all 15copies or substantial portions of the Software. 16 17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 19NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 22WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 24Except as contained in this notice, the names of the XFree86 Project and 25Silicon Motion shall not be used in advertising or otherwise to promote the 26sale, use or other dealings in this Software without prior written 27authorization from the XFree86 Project and SIlicon Motion. 28*/ 29 30#ifndef _REGSMI_H 31#define _REGSMI_H 32 33#ifndef PCI_CHIP_SMI501 34#define PCI_CHIP_SMI501 0x0501 35#endif 36 37#define SMI_LYNX_SERIES(chip) ((chip & 0xF0F0) == 0x0010) 38#define SMI_LYNX3D_SERIES(chip) ((chip & 0xF0F0) == 0x0020) 39#define SMI_COUGAR_SERIES(chip) ((chip & 0xF0F0) == 0x0030) 40#define SMI_LYNXEM_SERIES(chip) ((chip & 0xFFF0) == 0x0710) 41#define SMI_LYNXM_SERIES(chip) ((chip & 0xFF00) == 0x0700) 42#define SMI_MSOC_SERIES(chip) ((chip & 0xFF00) == 0x0500) 43 44/* Chip tags */ 45#define PCI_SMI_VENDOR_ID PCI_VENDOR_SMI 46#define SMI_UNKNOWN 0 47#define SMI_LYNX PCI_CHIP_SMI910 48#define SMI_LYNXE PCI_CHIP_SMI810 49#define SMI_LYNX3D PCI_CHIP_SMI820 50#define SMI_LYNXEM PCI_CHIP_SMI710 51#define SMI_LYNXEMplus PCI_CHIP_SMI712 52#define SMI_LYNX3DM PCI_CHIP_SMI720 53#define SMI_COUGAR3DR PCI_CHIP_SMI731 54#define SMI_MSOC PCI_CHIP_SMI501 55 56/* Mobile-System-on-a-Chip */ 57#define IS_MSOC(pSmi) ((pSmi)->Chipset == SMI_MSOC) 58 59/* I/O Functions */ 60static __inline__ CARD8 61VGAIN8_INDEX(SMIPtr pSmi, int indexPort, int dataPort, CARD8 index) 62{ 63 if (pSmi->IOBase) { 64 MMIO_OUT8(pSmi->IOBase, indexPort, index); 65 return(MMIO_IN8(pSmi->IOBase, dataPort)); 66 } else { 67 outb(pSmi->PIOBase + indexPort, index); 68 return(inb(pSmi->PIOBase + dataPort)); 69 } 70} 71 72static __inline__ void 73VGAOUT8_INDEX(SMIPtr pSmi, int indexPort, int dataPort, CARD8 index, CARD8 data) 74{ 75 if (pSmi->IOBase) { 76 MMIO_OUT8(pSmi->IOBase, indexPort, index); 77 MMIO_OUT8(pSmi->IOBase, dataPort, data); 78 } else { 79 outb(pSmi->PIOBase + indexPort, index); 80 outb(pSmi->PIOBase + dataPort, data); 81 } 82} 83 84static __inline__ CARD8 85VGAIN8(SMIPtr pSmi, int port) 86{ 87 if (pSmi->IOBase) { 88 return(MMIO_IN8(pSmi->IOBase, port)); 89 } else { 90 return(inb(pSmi->PIOBase + port)); 91 } 92} 93 94static __inline__ void 95VGAOUT8(SMIPtr pSmi, int port, CARD8 data) 96{ 97 if (pSmi->IOBase) { 98 MMIO_OUT8(pSmi->IOBase, port, data); 99 } else { 100 outb(pSmi->PIOBase + port, data); 101 } 102} 103 104#define WRITE_DPR(pSmi, dpr, data) \ 105 do { \ 106 MMIO_OUT32(pSmi->DPRBase, dpr, data); \ 107 DEBUG("DPR%02X = %08X\n", dpr, data); \ 108 } while (0) 109#define READ_DPR(pSmi, dpr) MMIO_IN32(pSmi->DPRBase, dpr) 110#define WRITE_VPR(pSmi, vpr, data) \ 111 do { \ 112 MMIO_OUT32(pSmi->VPRBase, vpr, data); \ 113 DEBUG("VPR%02X = %08X\n", vpr, data); \ 114 } while (0) 115#define READ_VPR(pSmi, vpr) MMIO_IN32(pSmi->VPRBase, vpr) 116#define WRITE_CPR(pSmi, cpr, data) \ 117 do { \ 118 MMIO_OUT32(pSmi->CPRBase, cpr, data); \ 119 DEBUG("CPR%02X = %08X\n", cpr, data); \ 120 } while (0) 121#define READ_CPR(pSmi, cpr) MMIO_IN32(pSmi->CPRBase, cpr) 122#define WRITE_FPR(pSmi, fpr, data) \ 123 do { \ 124 MMIO_OUT32(pSmi->FPRBase, fpr, data); \ 125 DEBUG("FPR%02X = %08X\n", fpr, data); \ 126 } while (0) 127#define READ_FPR(pSmi, fpr) MMIO_IN32(pSmi->FPRBase, fpr) 128#define WRITE_DCR(pSmi, dcr, data) \ 129 do { \ 130 MMIO_OUT32(pSmi->DCRBase, dcr, data); \ 131 DEBUG("DCR%02X = %08X\n", dcr, data); \ 132 } while (0) 133#define READ_DCR(pSmi, dcr) MMIO_IN32(pSmi->DCRBase, dcr) 134#define WRITE_SCR(pSmi, scr, data) \ 135 do { \ 136 MMIO_OUT32(pSmi->SCRBase, scr, data); \ 137 DEBUG("SCR%02X = %08X\n", scr, data); \ 138 } while (0) 139#define READ_SCR(pSmi, scr) MMIO_IN32(pSmi->SCRBase, scr) 140 141/* 2D Engine commands */ 142#define SMI_TRANSPARENT_SRC 0x00000100 143#define SMI_TRANSPARENT_DEST 0x00000300 144 145#define SMI_OPAQUE_PXL 0x00000000 146#define SMI_TRANSPARENT_PXL 0x00000400 147 148#define SMI_MONO_PACK_8 0x00001000 149#define SMI_MONO_PACK_16 0x00002000 150#define SMI_MONO_PACK_32 0x00003000 151 152#define SMI_ROP2_SRC 0x00008000 153#define SMI_ROP2_PAT 0x0000C000 154#define SMI_ROP3 0x00000000 155 156#define SMI_BITBLT 0x00000000 157#define SMI_RECT_FILL 0x00010000 158#define SMI_TRAPEZOID_FILL 0x00030000 159#define SMI_SHORT_STROKE 0x00060000 160#define SMI_BRESENHAM_LINE 0x00070000 161#define SMI_HOSTBLT_WRITE 0x00080000 162#define SMI_HOSTBLT_READ 0x00090000 163#define SMI_ROTATE_BLT 0x000B0000 164 165#define SMI_SRC_COLOR 0x00000000 166#define SMI_SRC_MONOCHROME 0x00400000 167 168#define SMI_GRAPHICS_STRETCH 0x00800000 169 170#define SMI_ROTATE_CW 0x01000000 171#define SMI_ROTATE_CCW 0x02000000 172 173#define SMI_MAJOR_X 0x00000000 174#define SMI_MAJOR_Y 0x04000000 175 176#define SMI_LEFT_TO_RIGHT 0x00000000 177#define SMI_RIGHT_TO_LEFT 0x08000000 178 179#define SMI_COLOR_PATTERN 0x40000000 180#define SMI_MONO_PATTERN 0x00000000 181 182#define SMI_QUICK_START 0x10000000 183#define SMI_START_ENGINE 0x80000000 184 185/* timeout value for engine waits */ 186#define MAXLOOP 0x100000 187 188/* Wait until 2d engine queue is empty */ 189#define WaitQueue() \ 190 do { \ 191 int loop = MAXLOOP; \ 192 \ 193 mem_barrier(); \ 194 if (IS_MSOC(pSmi)) { \ 195 /* 20:20 2D Engine FIFO Status. This bit is read-only. 196 * 0: FIFO not empty. 197 * 1: FIFO empty. 198 */ \ 199 while (loop-- && \ 200 (READ_SCR(pSmi, 0x0000) & (1 << 20)) == 0) \ 201 ; \ 202 } \ 203 else { \ 204 while (loop-- && \ 205 !(VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, \ 206 VGA_SEQ_DATA, 0x16) & 0x10)) \ 207 ; \ 208 } \ 209 if (loop <= 0) \ 210 SMI_GEReset(pScrn, 1, __LINE__, __FILE__); \ 211 } while (0) 212 213/* Wait until GP is idle */ 214#define WaitIdle() \ 215 do { \ 216 int loop = MAXLOOP; \ 217 \ 218 mem_barrier(); \ 219 if (IS_MSOC(pSmi)) { \ 220 MSOCCmdStatusRec status; \ 221 \ 222 /* bit 0: 2d engine idle if *not set* 223 * bit 1: 2d fifo empty if *set* 224 * bit 2: 2d setup idle if if *not set* 225 * bit 18: color conversion idle if *not set* 226 * bit 19: command fifo empty if *set* 227 * bit 20: 2d memory fifo empty idle if *set* 228 */ \ 229 for (status.value = READ_SCR(pSmi, CMD_STATUS); \ 230 loop && (status.f.engine || \ 231 !status.f.cmdfifo || \ 232 status.f.setup || \ 233 status.f.csc || \ 234 !status.f.cmdhif || \ 235 !status.f.memfifo); \ 236 status.value = READ_SCR(pSmi, CMD_STATUS), loop--) \ 237 ; \ 238 } \ 239 else { \ 240 int status; \ 241 \ 242 for (status = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, \ 243 VGA_SEQ_DATA, 0x16); \ 244 loop && (status & 0x18) != 0x10; \ 245 status = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, \ 246 VGA_SEQ_DATA, 0x16), loop--) \ 247 ; \ 248 } \ 249 if (loop <= 0) \ 250 SMI_GEReset(pScrn, 1, __LINE__, __FILE__); \ 251 } while (0) 252 253 254#define RGB8_PSEUDO (-1) 255#define RGB16_565 0 256#define RGB16_555 1 257#define RGB32_888 2 258 259/* register defines so we're not hardcoding numbers */ 260 261#define FPR00 0x0000 262 263/* video window formats - I=indexed, P=packed */ 264#define FPR00_FMT_8I 0x0 265#define FPR00_FMT_15P 0x1 266#define FPR00_FMT_16P 0x2 267#define FPR00_FMT_32P 0x3 268#define FPR00_FMT_24P 0x4 269#define FPR00_FMT_8P 0x5 270#define FPR00_FMT_YUV422 0x6 271#define FPR00_FMT_YUV420 0x7 272 273/* possible bit definitions for FPR00 - VWI = Video Window 1 */ 274#define FPR00_VWIENABLE 0x00000008 275#define FPR00_VWITILE 0x00000010 276#define FPR00_VWIFILTER2 0x00000020 277#define FPR00_VWIFILTER4 0x00000040 278#define FPR00_VWIKEYENABLE 0x00000080 279#define FPR00_VWIGDF_SHIFT 16 280#define FPR00_VWIGDENABLE 0x00080000 281#define FPR00_VWIGDTILE 0x00100000 282 283#define FPR00_MASKBITS 0x0000FFFF 284 285#define FPR04 0x0004 286#define FPR08 0x0008 287#define FPR0C 0x000C 288#define FPR10 0x0010 289#define FPR14 0x0014 290#define FPR18 0x0018 291#define FPR1C 0x001C 292#define FPR20 0x0020 293#define FPR24 0x0024 294#define FPR58 0x0058 295#define FPR5C 0x005C 296#define FPR68 0x0068 297#define FPRB0 0x00B0 298#define FPRB4 0x00B4 299#define FPRC4 0x00C4 300#define FPRCC 0x00CC 301 302#define FPR158 0x0158 303#define FPR158_MASK_MAXBITS 0x07FF 304#define FPR158_MASK_BOUNDARY 0x0800 305#define FPR15C 0x015C 306#define FPR15C_MASK_HWCCOLORS 0x0000FFFF 307#define FPR15C_MASK_HWCADDREN 0xFFFF0000 308#define FPR15C_MASK_HWCENABLE 0x80000000 309 310/* Maximum hardware cursor dimensions */ 311#define SMILYNX_MAX_CURSOR 32 312#define SMI501_MAX_CURSOR 64 313#define SMILYNX_CURSOR_SIZE 1024 314#define SMI501_CURSOR_SIZE 2048 315#if SMI_CURSOR_ALPHA_PLANE 316/* Stored in either 4:4:4:4 or 5:6:5 format */ 317# define SMI501_ARGB_CURSOR_SIZE \ 318 (SMI501_MAX_CURSOR * SMI501_MAX_CURSOR * 2) 319#endif 320 321/* HWCursor definitions for Panel AND CRT */ 322#define SMI501_MASK_HWCENABLE 0x80000000 323#define SMI501_MASK_MAXBITS 0x000007FF 324#define SMI501_MASK_BOUNDARY 0x00000800 325#define SMI501_HWCFBADDR_MASK 0x0CFFFFFF 326 327/* panel sizes returned by the bios */ 328 329#define PANEL_640x480 0x00 330#define PANEL_800x600 0x01 331#define PANEL_1024x768 0x02 332#define PANEL_1280x1024 0x03 333#define PANEL_1600x1200 0x04 334#define PANEL_1400x1050 0x0A 335 336 337#endif /* _REGSMI_H */ 338