sis_accel.h revision 72b676d7
172b676d7Smrg/* $XFree86$ */
272b676d7Smrg/* $XdotOrg$ */
372b676d7Smrg/*
472b676d7Smrg * 2D acceleration for 5597/5598 and 6326
572b676d7Smrg * Definitions for the SIS engine communication
672b676d7Smrg *
772b676d7Smrg * Copyright (C) 1998, 1999 by Alan Hourihane, Wigan, England.
872b676d7Smrg * Parts Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
972b676d7Smrg *
1072b676d7Smrg * Licensed under the following terms:
1172b676d7Smrg *
1272b676d7Smrg * Permission to use, copy, modify, distribute, and sell this software and its
1372b676d7Smrg * documentation for any purpose is hereby granted without fee, provided that
1472b676d7Smrg * the above copyright notice appears in all copies and that both that copyright
1572b676d7Smrg * notice and this permission notice appear in supporting documentation, and
1672b676d7Smrg * and that the name of the copyright holder not be used in advertising
1772b676d7Smrg * or publicity pertaining to distribution of the software without specific,
1872b676d7Smrg * written prior permission. The copyright holder makes no representations
1972b676d7Smrg * about the suitability of this software for any purpose.  It is provided
2072b676d7Smrg * "as is" without expressed or implied warranty.
2172b676d7Smrg *
2272b676d7Smrg * THE COPYRIGHT HOLDER DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
2372b676d7Smrg * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
2472b676d7Smrg * EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY SPECIAL, INDIRECT OR
2572b676d7Smrg * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
2672b676d7Smrg * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
2772b676d7Smrg * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
2872b676d7Smrg * PERFORMANCE OF THIS SOFTWARE.
2972b676d7Smrg *
3072b676d7Smrg * Authors:  Alan Hourihane <alanh@fairlite.demon.co.uk>,
3172b676d7Smrg *           Mike Chapman <mike@paranoia.com>,
3272b676d7Smrg *           Juanjo Santamarta <santamarta@ctv.es>,
3372b676d7Smrg *           Mitani Hiroshi <hmitani@drl.mei.co.jp>,
3472b676d7Smrg *           David Thomas <davtom@dream.org.uk>,
3572b676d7Smrg *	     Thomas Winischhofer <thomas@winischhofer.net>.
3672b676d7Smrg */
3772b676d7Smrg
3872b676d7Smrg
3972b676d7Smrg/* Definitions for the SIS engine communication. ------------------------------------ */
4072b676d7Smrg
4172b676d7Smrg/* For pre-530 chipsets only!!! */
4272b676d7Smrg
4372b676d7Smrg/* Engine Registers for 1st generation engines (5597/5598/6326) */
4472b676d7Smrgconst int sisReg32MMIO[] = {
4572b676d7Smrg            0x8280,0x8284,0x8288,0x828C,0x8290,0x8294,
4672b676d7Smrg            0x8298,0x829C,0x82A0,0x82A4,0x82A8,0x82AC
4772b676d7Smrg};
4872b676d7Smrg
4972b676d7Smrg#define BR(x) sisReg32MMIO[x]
5072b676d7Smrg
5172b676d7Smrg/* These are done using Memory Mapped IO, of the registers */
5272b676d7Smrg/*
5372b676d7Smrg * Modified for Sis by Xavier Ducoin (xavier@rd.lectra.fr)
5472b676d7Smrg *
5572b676d7Smrg */
5672b676d7Smrg
5772b676d7Smrg/* Command Reg 0 (0x82aa, [15:0]) */
5872b676d7Smrg#define sisSRCBG            0x0000   /* source select */
5972b676d7Smrg#define sisSRCFG            0x0001
6072b676d7Smrg#define sisSRCVIDEO         0x0002
6172b676d7Smrg#define sisSRCSYSTEM        0x0003
6272b676d7Smrg
6372b676d7Smrg#define sisPATFG            0x0004   /* pattern select */
6472b676d7Smrg#define sisPATREG           0x0008
6572b676d7Smrg#define sisPATBG            0x0000
6672b676d7Smrg
6772b676d7Smrg#define sisLEFT2RIGHT       0x0010   /* Direction select */
6872b676d7Smrg#define sisRIGHT2LEFT       0x0000
6972b676d7Smrg#define sisTOP2BOTTOM       0x0020
7072b676d7Smrg#define sisBOTTOM2TOP       0x0000
7172b676d7Smrg#define sisXINCREASE        sisLEFT2RIGHT
7272b676d7Smrg#define sisYINCREASE        sisTOP2BOTTOM
7372b676d7Smrg
7472b676d7Smrg#define sisCLIPENABL        0x0040   /* Clipping select */
7572b676d7Smrg#define sisCLIPINTRN        0x0080
7672b676d7Smrg#define sisCLIPEXTRN        0x0000
7772b676d7Smrg
7872b676d7Smrg#define sisCMDBLT           0x0000   /* Command select */
7972b676d7Smrg#define sisCMDBLTMSK        0x0100
8072b676d7Smrg#define sisCMDCOLEXP        0x0200
8172b676d7Smrg#define sisCMDLINE          0x0300
8272b676d7Smrg#define sisFLGECOLEXP       0x2000
8372b676d7Smrg#define sisCMDECOLEXP       (sisCMDCOLEXP | sisFLGECOLEXP)
8472b676d7Smrg
8572b676d7Smrg#define sisLASTPIX          0x0800   /* Line parameters */
8672b676d7Smrg#define sisXMAJOR           0x0400
8772b676d7Smrg
8872b676d7Smrg
8972b676d7Smrg/* Macros to do useful things with the SIS BitBLT engine */
9072b676d7Smrg
9172b676d7Smrg#define sisBLTSync \
9272b676d7Smrg  while(SIS_MMIO_IN16(pSiS->IOBase, BR(10) + 2) & 0x4000) {}
9372b676d7Smrg
9472b676d7Smrg/* According to SiS 6326 2D programming guide, 16 bits position at   */
9572b676d7Smrg/* 0x82A8 returns queue free. But this don't work, so don't wait     */
9672b676d7Smrg/* anything when turbo-queue is enabled. If there are frequent syncs */
9772b676d7Smrg/* this should work. But not for xaa_benchmark :-(     */
9872b676d7Smrg
9972b676d7Smrg/* TW: Bit 16 only applies to the hardware queue, not the software
10072b676d7Smrg *     (=turbo) queue.
10172b676d7Smrg */
10272b676d7Smrg
10372b676d7Smrg#define sisBLTWAIT \
10472b676d7Smrg  if(!pSiS->TurboQueue) { \
10572b676d7Smrg    while(SIS_MMIO_IN16(pSiS->IOBase, BR(10) + 2) & 0x4000) {} \
10672b676d7Smrg  } else { \
10772b676d7Smrg    sisBLTSync \
10872b676d7Smrg  }
10972b676d7Smrg
11072b676d7Smrg#define sisSETPATREG() \
11172b676d7Smrg   ((UChar *)(pSiS->IOBase + BR(11)))
11272b676d7Smrg
11372b676d7Smrg#define sisSETPATREGL() \
11472b676d7Smrg   ((ULong *)(pSiS->IOBase + BR(11)))
11572b676d7Smrg
11672b676d7Smrg/* trigger command */
11772b676d7Smrg#define sisSETCMD(op) \
11872b676d7Smrg  { \
11972b676d7Smrg  ULong temp; \
12072b676d7Smrg  SIS_MMIO_OUT16(pSiS->IOBase, BR(10) + 2, op); \
12172b676d7Smrg  temp = SIS_MMIO_IN32(pSiS->IOBase, BR(10)); \
12272b676d7Smrg  (void)temp; \
12372b676d7Smrg  }
12472b676d7Smrg
12572b676d7Smrg/* set foreground color and fg ROP */
12672b676d7Smrg#define sisSETFGROPCOL(rop, color) \
12772b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(4), ((rop << 24) | (color & 0xFFFFFF)));
12872b676d7Smrg
12972b676d7Smrg/* set background color and bg ROP */
13072b676d7Smrg#define sisSETBGROPCOL(rop, color) \
13172b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(5), ((rop << 24) | (color & 0xFFFFFF)));
13272b676d7Smrg
13372b676d7Smrg/* background color */
13472b676d7Smrg#define sisSETBGCOLOR(bgColor) \
13572b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(5), (bgColor));
13672b676d7Smrg
13772b676d7Smrg/* foreground color */
13872b676d7Smrg#define sisSETFGCOLOR(fgColor) \
13972b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(4), (fgcolor));
14072b676d7Smrg
14172b676d7Smrg/* ROP */
14272b676d7Smrg#define sisSETROPFG(op) \
14372b676d7Smrg   SIS_MMIO_OUT8(pSiS->IOBase, BR(4) + 3, op);
14472b676d7Smrg
14572b676d7Smrg#define sisSETROPBG(op) \
14672b676d7Smrg  SIS_MMIO_OUT8(pSiS->IOBase, BR(5) + 3, op);
14772b676d7Smrg
14872b676d7Smrg#define sisSETROP(op) \
14972b676d7Smrg   sisSETROPFG(op); sisSETROPBG(op);
15072b676d7Smrg
15172b676d7Smrg/* source and dest address */
15272b676d7Smrg#define sisSETSRCADDR(srcAddr) \
15372b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(0), (srcAddr & 0x3FFFFFL));
15472b676d7Smrg
15572b676d7Smrg#define sisSETDSTADDR(dstAddr) \
15672b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(1), (dstAddr & 0x3FFFFFL));
15772b676d7Smrg
15872b676d7Smrg/* pitch */
15972b676d7Smrg#define sisSETPITCH(srcPitch,dstPitch) \
16072b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(2), ((((dstPitch) & 0xFFFF) << 16) | ((srcPitch) & 0xFFFF)));
16172b676d7Smrg
16272b676d7Smrg#define sisSETSRCPITCH(srcPitch) \
16372b676d7Smrg  SIS_MMIO_OUT16(pSiS->IOBase, BR(2), ((srcPitch) & 0xFFFF));
16472b676d7Smrg
16572b676d7Smrg#define sisSETDSTPITCH(dstPitch) \
16672b676d7Smrg  SIS_MMIO_OUT16(pSiS->IOBase, BR(2) + 2, ((dstPitch) & 0xFFFF));
16772b676d7Smrg
16872b676d7Smrg/* Height and width
16972b676d7Smrg * According to SIS 2D Engine Programming Guide
17072b676d7Smrg * height -1, width - 1 independant of Bpp
17172b676d7Smrg */
17272b676d7Smrg#define sisSETHEIGHTWIDTH(Height, Width) \
17372b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(3), ((((Height) & 0xFFFF) << 16) | ((Width) & 0xFFFF)));
17472b676d7Smrg
17572b676d7Smrg/* Clipping */
17672b676d7Smrg#define sisSETCLIPTOP(x, y) \
17772b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(8), ((((y) & 0xFFFF) << 16) | ((x) & 0xFFFF)));
17872b676d7Smrg
17972b676d7Smrg#define sisSETCLIPBOTTOM(x, y) \
18072b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(9), ((((y) & 0xFFFF) << 16) | ((x) & 0xFFFF)));
18172b676d7Smrg
18272b676d7Smrg/* Line drawing */
18372b676d7Smrg#define sisSETXStart(XStart) \
18472b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(0), ((XStart) & 0xFFFF));
18572b676d7Smrg
18672b676d7Smrg#define sisSETYStart(YStart) \
18772b676d7Smrg  SIS_MMIO_OUT32(pSiS->IOBase, BR(1), ((YStart) & 0xFFFF));
18872b676d7Smrg
18972b676d7Smrg#define sisSETLineMajorCount(MajorAxisCount) \
19072b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(3), ((MajorAxisCount) & 0xFFFF));
19172b676d7Smrg
19272b676d7Smrg#define sisSETLineSteps(K1,K2) \
19372b676d7Smrg   SIS_MMIO_OUT32(pSiS->IOBase, BR(6), ((((K1) & 0xFFFF) << 16) | ((K2) & 0xFFFF)));
19472b676d7Smrg
19572b676d7Smrg#define sisSETLineErrorTerm(ErrorTerm) \
19672b676d7Smrg   SIS_MMIO_OUT16(pSiS->IOBase, BR(7), (ErrorTerm));
197