vb_init.c revision 098ad5bd
1/* Copyright (C) 2003-2006 by XGI Technology, Taiwan. 2 * 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation on the rights to use, copy, modify, merge, 9 * publish, distribute, sublicense, and/or sell copies of the Software, 10 * and to permit persons to whom the Software is furnished to do so, 11 * subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR 21 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 */ 26#ifdef HAVE_CONFIG_H 27#include "config.h" 28#endif 29 30#include <unistd.h> 31#include "osdef.h" 32#include "vgatypes.h" 33 34 35#ifdef LINUX_KERNEL 36#include <linux/version.h> 37#include <linux/types.h> 38#include <linux/delay.h> /* udelay */ 39#include "XGIfb.h" 40#endif 41 42#include "vb_def.h" 43#include "vb_struct.h" 44#include "vb_setmode.h" 45#include "vb_init.h" 46#include "vb_ext.h" 47 48#ifdef LINUX_XF86 49#include "xf86.h" 50#include "xf86PciInfo.h" 51#include "xgi.h" 52#include "xgi_regs.h" 53#endif 54 55#ifdef LINUX_KERNEL 56#include <asm/io.h> 57#include <linux/types.h> 58#endif 59 60 61 62 63static UCHAR XGINew_ChannelAB; 64static UCHAR XGINew_DataBusWidth; 65 66USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48}, 67 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44}, 68 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40}, 69 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32}, 70 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30}, 71 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28}, 72 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24}, 73 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10}, 74 {0x09,0x08,0x01,0x01,0x00}}; 75 76static const USHORT XGINew_SDRDRAM_TYPE[13][5]= 77{ 78 { 2,12, 9,64,0x35}, 79 { 1,13, 9,64,0x44}, 80 { 2,12, 8,32,0x31}, 81 { 2,11, 9,32,0x25}, 82 { 1,12, 9,32,0x34}, 83 { 1,13, 8,32,0x40}, 84 { 2,11, 8,16,0x21}, 85 { 1,12, 8,16,0x30}, 86 { 1,11, 9,16,0x24}, 87 { 1,11, 8, 8,0x20}, 88 { 2, 9, 8, 4,0x01}, 89 { 1,10, 8, 4,0x10}, 90 { 1, 9, 8, 2,0x00} 91}; 92 93static const USHORT XGINew_DDRDRAM_TYPE[4][5]= 94{ 95 { 2,12, 9,64,0x35}, 96 { 2,12, 8,32,0x31}, 97 { 2,11, 8,16,0x21}, 98 { 2, 9, 8, 4,0x01} 99}; 100 101static const USHORT XGINew_DDRDRAM_TYPE340[4][5]= 102{ 103 { 2,13, 9,64,0x45}, 104 { 2,12, 9,32,0x35}, 105 { 2,12, 8,16,0x31}, 106 { 2,11, 8, 8,0x21} 107}; 108 109/* Jong 10/05/2007; merge code */ 110USHORT XGINew_DDRDRAM_TYPE20[12][5]= 111{ 112{ 2,14,11,128,0x5D}, 113{ 2,14,10,64,0x59}, 114{ 2,13,11,64,0x4D}, 115{ 2,14, 9,32,0x55}, 116{ 2,13,10,32,0x49}, 117{ 2,12,11,32,0x3D}, 118{ 2,14, 8,16,0x51}, 119{ 2,13, 9,16,0x45}, 120{ 2,12,10,16,0x39}, 121{ 2,13, 8, 8,0x41}, 122{ 2,12, 9, 8,0x35}, 123{ 2,12, 8, 4,0x31} 124}; 125 126static void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 127static void XGINew_SetDRAMSize_XG45(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 128static void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 129static void XGINew_SetDRAMModeRegister340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 130static void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO, USHORT, 131 PVB_DEVICE_INFO); 132static void XGINew_SetDRAMDefaultRegisterXG45(PXGI_HW_DEVICE_INFO, USHORT, 133 PVB_DEVICE_INFO); 134static UCHAR XGINew_Get340DRAMType(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 135 136static int XGINew_SetDDRChannel(int index, UCHAR ChannelNo, 137 UCHAR XGINew_ChannelAB, const USHORT DRAMTYPE_TABLE[][5], 138 PVB_DEVICE_INFO pVBInfo); 139 140static void XGINew_SetDRAMSizingType(int index , 141 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 142static USHORT XGINew_SetDRAMSizeReg(int index, 143 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 144 145static int XGINew_SetRank(int index, UCHAR RankNo, UCHAR XGINew_ChannelAB, 146 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 147 148static int XGINew_CheckRanks(int RankNo, int index, 149 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 150static int XGINew_CheckRank(int RankNo, int index, 151 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 152static int XGINew_CheckDDRRank(int RankNo, int index, 153 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 154static int XGINew_CheckDDRRanks(int RankNo, int index, 155 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 156 157static int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5], 158 PVB_DEVICE_INFO pVBInfo); 159static int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5], 160 PVB_DEVICE_INFO pVBInfo); 161 162static int XGINew_DDRSizing340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 163static int XGINew_DDRSizingXG45(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 164static int XGINew_SDRSizing(PVB_DEVICE_INFO); 165static int XGINew_DDRSizing(PVB_DEVICE_INFO); 166 167/* Jong 10/05/2007; merge code */ 168static void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ; 169static UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo); 170static void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ; 171static UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo); 172 173static void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo); 174static void XGINew_SDR_MRS(PVB_DEVICE_INFO pVBInfo); 175static void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 176 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 177static void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 178 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 179static void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 180 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 181static void XGINew_DDR1x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 182 USHORT Port, PVB_DEVICE_INFO pVBInfo); 183static void XGINew_DDR2x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 184 USHORT Port, PVB_DEVICE_INFO pVBInfo); 185static void XGINew_DDR2_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 186 USHORT Port, PVB_DEVICE_INFO pVBInfo); 187 188static void XGINew_DisableChannelInterleaving(int index, 189 const USHORT XGINew_DDRDRAM_TYPE[][5], PVB_DEVICE_INFO pVBInfo); 190 191static void DualChipInit(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 192 193static void XGINew_DisableRefresh(PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO); 194static void XGINew_EnableRefresh(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 195 196static void XGINew_Delay15us(ULONG); 197static void SetPowerConsume(PXGI_HW_DEVICE_INFO, USHORT); 198static void XGINew_DDR1x_MRS_XG20(USHORT, PVB_DEVICE_INFO); 199static void XGINew_SetDRAMModeRegister_XG20(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 200static void XGINew_ChkSenseStatus(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 201 202static int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr, 203 PVB_DEVICE_INFO pVBInfo); 204static int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr, 205 PVB_DEVICE_INFO pVBInfo); 206static UCHAR XGINew_CheckFrequence(PVB_DEVICE_INFO pVBInfo); 207static void XGINew_CheckChannel(PXGI_HW_DEVICE_INFO HwDeviceExtension, 208 PVB_DEVICE_INFO pVBInfo); 209 210static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/ 211static ULONG UNIROM; /* UNIROM */ 212 213 214#ifdef LINUX_KERNEL 215void DelayUS(ULONG MicroSeconds) 216{ 217 udelay(MicroSeconds); 218} 219#endif 220 221/* --------------------------------------------------------------------- */ 222/* Function : XGIInitNew */ 223/* Input : */ 224/* Output : */ 225/* Description : */ 226/* --------------------------------------------------------------------- */ 227BOOLEAN XGIInitNew(PXGI_HW_DEVICE_INFO HwDeviceExtension, 228 PVB_DEVICE_INFO pVBInfo) 229{ 230#ifndef LINUX_XF86 231 USHORT Mclockdata[ 30 ] , Eclockdata[ 30 ] ; 232 UCHAR j , SR11 , SR17 = 0 , SR18 = 0 , SR19 = 0 ; 233 UCHAR CR37 = 0 , CR38 = 0 , CR79 = 0 , CR7A = 0 , 234 CR7B = 0 , CR36 = 0 , CR78 = 0 , CR3C = 0 , 235 CR3D = 0 , CR3E = 0 , CR3F = 0 , CR35 = 0 ; 236#endif 237 UCHAR i , temp = 0 , temp1 , 238 VBIOSVersion[ 5 ] ; 239 ULONG base,ChipsetID,VendorID,GraphicVendorID; 240 PUCHAR volatile pVideoMemory; 241 242 /* ULONG j, k ; */ 243 244 PXGI_DSReg pSR ; 245 246 ULONG Temp ; 247 248 249 XGINew_InitVBIOSData(HwDeviceExtension, pVBInfo); 250 251 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr; 252 253 254 Newdebugcode( 0x99 ) ; 255 256 /* if ( pVBInfo->ROMAddr == 0 ) */ 257 /* return( FALSE ) ; */ 258 259 if ( pVBInfo->FBAddr == 0 ) 260 return( FALSE ) ; 261 262 if ( pVBInfo->BaseAddr == 0 ) 263 return( FALSE ) ; 264 265 XGI_SetRegByte((XGIIOADDRESS) ( USHORT )( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */ 266 267 268 if ( !HwDeviceExtension->bIntegratedMMEnabled ) 269 return( FALSE ) ; /* alan */ 270 271 272 273 XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ; 274 275 VBIOSVersion[ 4 ] = 0x0 ; 276 277 278 /* ReadVBIOSData */ 279 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 280 281 /* 1.Openkey */ 282 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x05 , 0x86 ) ; 283 284 285 286 /* 2.Reset Extended register */ 287 288 for( i = 0x06 ; i < 0x20 ; i++ ) 289 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 290 291 for( i = 0x21 ; i <= 0x27 ; i++ ) 292 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 293 294 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */ 295 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; */ 296 297 298 if(( HwDeviceExtension->jChipType == XG20 ) || ( HwDeviceExtension->jChipType >= XG40)) 299 { 300 for( i = 0x31 ; i <= 0x3B ; i++ ) 301 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 302 } 303 else 304 { 305 for( i = 0x31 ; i <= 0x3D ; i++ ) 306 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 307 } 308 309 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */ 310 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B , 0xC0 ) ; 311 312 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */ 313 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; */ 314 315 for( i = 0x79 ; i <= 0x7C ; i++ ) 316 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */ 317 318 /* Jong 10/01/2007; SetDefPCIRegs */ /* alan 12/07/2006 */ 319 if ( HwDeviceExtension->jChipType == XG27 ) 320 { 321 for( i = 0xD0 ; i <= 0xDB ; i++ ) 322 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRD0[i-0xd0] ) ; 323 for( i = 0xDE ; i <= 0xDF ; i++ ) 324 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRDE[i-0xdE] ) ; 325 } 326 327 328 if ( HwDeviceExtension->jChipType >= XG20 ) 329 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x97, pVBInfo->CR97); 330 331 /* 3.SetMemoryClock */ 332 if (!(pVBInfo->SoftSetting & SoftDRAMType)) { 333 if (( HwDeviceExtension->jChipType == XG20 )||( HwDeviceExtension->jChipType == XG21 )||( HwDeviceExtension->jChipType == XG27 )) 334 { 335 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 336 } 337 else if (HwDeviceExtension->jChipType == XG45) 338 { 339 temp = 0x02 ; 340 } 341 else 342 { 343 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ; 344 } 345 } 346 347 348 if ( HwDeviceExtension->jChipType == XG20 ) 349 XGINew_RAMType = temp & 0x01 ; 350 else 351 { 352 XGINew_RAMType = temp & 0x03 ; /* alan */ 353 } 354 355 /* Get DRAM type */ 356 if ( HwDeviceExtension->jChipType == XG45 ) 357 { } 358 else if ( HwDeviceExtension->jChipType >= XG40 ) 359 XGINew_RAMType = ( int )XGINew_Get340DRAMType( HwDeviceExtension , pVBInfo) ; 360 361 if ( UNIROM == 1 ) XGINew_RAMType = 0; 362 363 if ( HwDeviceExtension->jChipType < XG40 ) 364 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 365 366 /* 4.SetDefExt1Regs begin */ 367 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x07, pVBInfo->SR07); 368 369 /* Jong 10/01/2007; add for ??? */ 370 if ( HwDeviceExtension->jChipType == XG27 ) 371 { 372 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ; 373 XGI_SetReg( (XGIIOADDRESS)pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ; 374 } 375 376 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x11, 0x0F); 377 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x1F, pVBInfo->SR1F); 378 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0x20); */ 379 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */ 380 381 /* Jong 10/01/2007; added for ??? */ 382 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */ 383 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */ 384 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ; 385 386 /* SR11 = 0x0F ; */ 387 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x11 , SR11 ) ; */ 388 389 390 if ( (HwDeviceExtension->jChipType != XG20) 391 &&(HwDeviceExtension->jChipType != XG21) 392 &&(HwDeviceExtension->jChipType != XG27) 393 &&(HwDeviceExtension->jChipType != XG45) ) /* kuku 2004/06/25 */ 394 { 395 /* Set AGP Rate */ 396 temp1 = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ; 397 temp1 &= 0x02 ; 398 if ( temp1 == 0x02 ) 399 { 400 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x80000000 ) ; 401 ChipsetID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 402 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x8000002C ) ; 403 VendorID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 404 VendorID &= 0x0000FFFF ; 405 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x8001002C ) ; 406 GraphicVendorID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 407 GraphicVendorID &= 0x0000FFFF; 408 409 if ( ChipsetID == 0x7301039 ) 410 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x09 ) ; 411 412 ChipsetID &= 0x0000FFFF ; 413 414 if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) ) 415 { 416 if ( ChipsetID == 0x1106 ) 417 { 418 if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) ) 419 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0D ) ; 420 else 421 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ; 422 } 423 else 424 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ; 425 } 426 } 427 428 if ( HwDeviceExtension->jChipType >= XG40 ) 429 { 430 /* Set AGP customize registers (in SetDefAGPRegs) Start */ 431 for( i = 0x47 ; i <= 0x4C ; i++ ) 432 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ; 433 434 for( i = 0x70 ; i <= 0x71 ; i++ ) 435 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ; 436 437 for( i = 0x74 ; i <= 0x77 ; i++ ) 438 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ; 439 /* Set AGP customize registers (in SetDefAGPRegs) End */ 440 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */ 441 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x80000000 ) ; 442 ChipsetID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 443 if ( ChipsetID == 0x25308086 ) 444 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x77 , 0xF0 ) ; 445 446 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */ 447 Temp >>= 20 ; 448 Temp &= 0xF ; 449 450 if ( Temp == 1 ) 451 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */ 452 } 453 454 if ( HwDeviceExtension->jChipType < XG40 ) 455 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ; 456 } /* != XG20 */ 457 458 /* Set PCI */ 459 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x23, pVBInfo->SR23); 460 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x24, pVBInfo->SR24); 461 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]); 462 463 if ( (HwDeviceExtension->jChipType != XG20) && 464 (HwDeviceExtension->jChipType != XG21) && 465 (HwDeviceExtension->jChipType != XG27) ) /* kuku 2004/06/25 */ 466 { 467 /* Set VB */ 468 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ; 469 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */ 470 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port , 0x00 , 0x00 ) ; 471 temp1 = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */ 472 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ; 473 474 475 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port, 0x02, 476 pVBInfo->CRT2Data_1_2); 477 478 479 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */ 480 } /* != XG20 */ 481 482 483 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x27 , 0x1F ) ; 484 485 /* Not DDR */ 486 if ((HwDeviceExtension->jChipType == XG42) 487 && XGINew_Get340DRAMType(HwDeviceExtension, pVBInfo) != 0) { 488 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, (pVBInfo->SR31 & 0x3F) | 0x40); 489 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, (pVBInfo->SR32 & 0xFC) | 0x01); 490 } 491 else { 492 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, pVBInfo->SR31); 493 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, pVBInfo->SR32); 494 } 495 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x33, pVBInfo->SR33); 496 497 498 499 if ( HwDeviceExtension->jChipType >= XG40 ) 500 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); 501 502 if ( (HwDeviceExtension->jChipType != XG20) && 503 (HwDeviceExtension->jChipType != XG21) && 504 (HwDeviceExtension->jChipType != XG27) ) /* kuku 2004/06/25 */ 505 { 506 if ( XGI_BridgeIsOn( pVBInfo ) == 1 ) 507 { 508 { 509 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part2Port, 0x00, 0x1C); 510 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0D, pVBInfo->CRT2Data_4_D); 511 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0E, pVBInfo->CRT2Data_4_E); 512 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x10, pVBInfo->CRT2Data_4_10); 513 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0F, 0x3F); 514 } 515 516 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ; 517 } 518 } /* != XG20 */ 519 520 if ( HwDeviceExtension->jChipType < XG40 ) 521 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x83 , 0x00 ) ; 522 523 524 /* Jong 10/01/2007; added for ??? */ 525 if ( HwDeviceExtension->bSkipSense == FALSE ) 526 { 527 XGI_SenseCRT1(pVBInfo) ; 528 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */ 529 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) ) 530 { 531 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */ 532 } 533 if ( HwDeviceExtension->jChipType == XG21 ) 534 { 535 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 536 temp = GetXG21FPBits( pVBInfo ) ; 537 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ; 538 } 539 if ( HwDeviceExtension->jChipType == XG27 ) 540 { 541 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 542 temp = GetXG27FPBits( pVBInfo ) ; 543 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ; 544 } 545 } 546 547 if ( HwDeviceExtension->jChipType >= XG40 ) 548 { 549 if (HwDeviceExtension->jChipType == XG45) 550 XGINew_SetDRAMDefaultRegisterXG45( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ; 551 else 552 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ; 553 554 if ( HwDeviceExtension->bSkipDramSizing == TRUE ) 555 { 556 pSR = HwDeviceExtension->pSR ; 557 if ( pSR!=NULL ) 558 { 559 while( pSR->jIdx != 0xFF ) 560 { 561 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ; 562 pSR++ ; 563 } 564 } 565 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 566 } /* SkipDramSizing */ 567 else 568 { 569/* if ( HwDeviceExtension->jChipType == XG20 ) 570 { 571 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ; 572 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ; 573 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x20 , 0x20 ) ; 574 } 575 else*/ 576 if ( HwDeviceExtension->jChipType == XG45 ) 577 XGINew_SetDRAMSize_XG45( HwDeviceExtension , pVBInfo) ; 578 else 579 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ; 580 } 581 } /* XG40 */ 582 583 584 585 586 /* SetDefExt2Regs begin */ 587/* 588 AGP = 1 ; 589 temp =( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ; 590 temp &= 0x30 ; 591 if ( temp == 0x30 ) 592 AGP = 0 ; 593 594 if ( AGP == 0 ) 595 pVBInfo->SR21 &= 0xEF ; 596 597 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , pVBInfo->SR21 ) ; 598 if ( AGP == 1 ) 599 pVBInfo->SR22 &= 0x20; 600 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x22 , pVBInfo->SR22 ) ; 601*/ 602 603 base = 0x80000000; 604 XGI_SetRegLong(0xcf8, base); 605 Temp = (XGI_GetRegLong(0xcfc) & 0x0000FFFF); 606 if (Temp == 0x1039) { 607 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22 & 0xFE); 608 } 609 else { 610 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22); 611 } 612 613 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x21, pVBInfo->SR21); 614 615 if ( HwDeviceExtension->jChipType == XG40 ) /* Initialize seconary chip */ 616 { 617 if ( CheckDualChip(pVBInfo) ) 618 DualChipInit( HwDeviceExtension , pVBInfo) ; 619 /* SetDefExt2Regs end */ 620 } 621 622 /* Jong 10/01/2007; be removed and recoded */ 623#if 0 624 if ( HwDeviceExtension->bSkipSense == FALSE ) 625 { 626 XGI_SenseCRT1(pVBInfo) ; 627 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */ 628 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */ 629 } 630#endif 631 632 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ; 633 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ; 634 635 Newdebugcode( 0x88 ) ; 636 637 /* Johnson@062403. To save time for power management. */ 638 /* DelayMS(1000); */ 639 /* ~Johnson@062403. */ 640 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , 0x28 ) ; //0207 temp */ 641 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x36 , 0x02 ) ; //0207 temp */ 642 643 return( TRUE ) ; 644} /* end of init */ 645 646 647 648/* --------------------------------------------------------------------- */ 649/* Function : DualChipInit */ 650/* Input : */ 651/* Output : */ 652/* Description : Initialize the secondary chip. */ 653/* --------------------------------------------------------------------- */ 654void DualChipInit( PXGI_HW_DEVICE_INFO HwDeviceExtension ,PVB_DEVICE_INFO pVBInfo) 655{ 656#ifdef LINUX_XF86 657 USHORT BaseAddr2nd = (USHORT)(ULONG)HwDeviceExtension->pj2ndIOAddress ; 658#else 659 USHORT BaseAddr2nd = (USHORT)HwDeviceExtension->pj2ndIOAddress ; 660#endif 661 USHORT XGINew_P3C3 = pVBInfo->BaseAddr + VIDEO_SUBSYSTEM_ENABLE_PORT ; 662 USHORT XGINew_P3CC = pVBInfo->BaseAddr + MISC_OUTPUT_REG_READ_PORT ; 663 USHORT XGINew_2ndP3C3 = BaseAddr2nd + VIDEO_SUBSYSTEM_ENABLE_PORT ; 664 USHORT XGINew_2ndP3D4 = BaseAddr2nd + CRTC_ADDRESS_PORT_COLOR ; 665 USHORT XGINew_2ndP3C4 = BaseAddr2nd + SEQ_ADDRESS_PORT ; 666 USHORT XGINew_2ndP3C2 = BaseAddr2nd + MISC_OUTPUT_REG_WRITE_PORT ; 667 ULONG Temp ; 668 UCHAR tempal , i ; 669 670 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 671 pVBInfo->BaseAddr = (USHORT)HwDeviceExtension->pjIOAddress ; 672 /* Programming Congiguration Space in Secondary Chip */ 673 /* set CRA1 D[6] = 1 */ 674 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0xBF , 0x40 ) ; 675 676 /* Write 2nd Chip Configuration Info into Configuration Space */ 677 /* Command CNFG04 */ 678 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , PCI_COMMAND , 0 , &Temp ) ; /* Get */ 679 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , PCI_COMMAND + 0x80 , 1 , &Temp ) ; /* Set */ 680 /* Latency Timer CNFG0C */ 681 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x0c , 0 , &Temp ) ; /* Get */ 682 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x0c + 0x80 , 1 , &Temp ) ; /* Set */ 683 /* Linear space */ 684 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x10 , 0 , &Temp ) ; /* Get */ 685 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x10 + 0x80 , 1 , &Temp ) ; /* Set */ 686 /* MMIO space */ 687 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x14 , 0 , &Temp ) ; /* Get */ 688 Temp += 0x40000; 689 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x14 + 0x80 , 1 , &Temp ) ; /* Set */ 690 /* Relocated IO space */ 691 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x18 , 0 , &Temp ) ; /* Get */ 692 Temp += 0x80; 693 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x18 + 0x80 , 1 , &Temp ) ; /* Set */ 694 /* Miscellaneous reg(input port 3cch,output port 3c2h) */ 695 tempal = XGI_GetRegByte((XGIIOADDRESS) XGINew_P3CC ) ; /* 3cc */ 696 XGI_SetRegByte((XGIIOADDRESS) XGINew_2ndP3C2 , tempal ) ; 697 /* VGA enable reg(port 3C3h) */ 698 tempal = XGI_GetRegByte((XGIIOADDRESS) XGINew_P3C3 ) ; /* 3c3 */ 699 XGI_SetRegByte((XGIIOADDRESS) XGINew_2ndP3C3 , tempal ) ; 700 SetPowerConsume ( HwDeviceExtension , XGINew_2ndP3D4); 701 /* ----- CRA0=42, CRA1=81, CRA2=60, CRA3=20, CRA4=50, CRA5=40, CRA8=88 -----// */ 702 /* ----- CRA9=10, CRAA=80, CRAB=01, CRAC=F1, CRAE=80, CRAF=45, CRB7=24 -----// */ 703 /* primary chip */ 704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA0 , 0x72 ) ; 705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0x81 ) ; 706 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA2 , 0x60 ) ; 707 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA3 , 0x20 ) ; 708 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA4 , 0x50 ) ; 709 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA5 , 0x40 ) ; 710 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA8 , 0x88 ) ; 711 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA9 , 0x10 ) ; 712 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAA , 0x80 ) ; 713 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAB , 0x01 ) ; 714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAC , 0xF1 ) ; 715 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAE , 0x80 ) ; 716 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAF , 0x45 ) ; 717 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xB7 , 0x24 ) ; 718 719 /* secondary chip */ 720 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA0 , 0x72 ) ; 721 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA1 , 0x81 ) ; 722 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA2 , 0x60 ) ; 723 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA3 , 0x20 ) ; 724 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA4 , 0x50 ) ; 725 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA5 , 0x40 ) ; 726 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA8 , 0x88 ) ; 727 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA9 , 0x10 ) ; 728 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAA , 0x80 ) ; 729 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAB , 0x01 ) ; 730 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAC , 0xF1 ) ; 731 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAE , 0x80 ) ; 732 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAF , 0x45 ) ; 733 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xB7 , 0x24 ) ; 734 735 /* 06/20/2003 [christine] CRT threshold setting request */ 736 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x78 , 0x40 ) ; 737 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x79 , 0x0C ) ; 738 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7A , 0x34 ) ; 739 740 /* OpenKey in 2nd chip */ 741 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x05 , 0x86 ) ; 742 743 /* Set PCI registers */ 744 tempal = (UCHAR)XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x06 ) ; 745 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x06 , tempal ) ; 746 747 for( i = 0x20 ; i <= 0x25 ; i++ ) 748 { 749 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 750 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 751 } 752 for(i = 0x31; i <= 0x32; i++ ) 753 { 754 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 755 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 756 } 757 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , XGINew_2ndP3D4 , pVBInfo) ; 758 759 for(i = 0x13; i <= 0x14; i++ ) 760 { 761 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 762 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 763 } 764 765 /* Close key in 2nd chip */ 766 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x05 , 0x00 ) ; 767} 768 769 770 771 772/* ============== alan ====================== */ 773 774/* --------------------------------------------------------------------- */ 775/* Function : XGINew_Get340DRAMType */ 776/* Input : */ 777/* Output : */ 778/* Description : */ 779/* --------------------------------------------------------------------- */ 780UCHAR XGINew_Get340DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 781{ 782 UCHAR data, temp ; /* Jong 10/05/2007; merge code */ 783 784 if ( HwDeviceExtension->jChipType < XG20 ) 785 { 786 if (pVBInfo->SoftSetting & SoftDRAMType) { 787 return (pVBInfo->SoftSetting & 0x07); 788 } 789 else 790 { 791 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ; 792 793 if ( data == 0 ) 794 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ; 795 796 return( data ) ; 797 } 798 } 799 else if ( HwDeviceExtension->jChipType == XG27 ) 800 { 801 if ( pVBInfo->SoftSetting & SoftDRAMType ) 802 { 803 data = pVBInfo->SoftSetting & 0x07 ; 804 return( data ) ; 805 } 806 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ; 807 808 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ 809 data = 0 ; /*DDR*/ 810 else 811 data = 1 ; /*DDRII*/ 812 return( data ) ; 813 } 814 else if ( HwDeviceExtension->jChipType == XG21 ) 815 { 816 XGI_SetRegAND( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */ 817 DelayUS(800); 818 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */ 819 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */ 820 821 /* HOTPLUG_SUPPORT */ 822 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */ 823 if ( temp & 0x01 ) /* DVI read GPIOH */ 824 data = 1 ; /*DDRII*/ 825 else 826 data = 0 ; /*DDR*/ 827 828 /*~HOTPLUG_SUPPORT */ 829 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , 0x02 ) ; 830 return( data ) ; 831 } 832 else 833 { 834 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) & 0x01 ; 835 836 if ( data == 1 ) 837 data ++ ; 838 839 return( data ); 840 } 841} 842 843 844/* --------------------------------------------------------------------- */ 845/* Function : XGINew_Delay15us */ 846/* Input : */ 847/* Output : */ 848/* Description : */ 849/* --------------------------------------------------------------------- */ 850/* 851void XGINew_Delay15us(ULONG ulMicrsoSec) 852{ 853} 854*/ 855 856 857/* --------------------------------------------------------------------- */ 858/* Function : XGINew_SDR_MRS */ 859/* Input : */ 860/* Output : */ 861/* Description : */ 862/* --------------------------------------------------------------------- */ 863void XGINew_SDR_MRS(PVB_DEVICE_INFO pVBInfo) 864{ 865 USHORT data ; 866 867 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ; 868 data &= 0x3F ; /* SR16 D7=0,D6=0 */ 869 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */ 870 /* XGINew_Delay15us( 0x100 ) ; */ 871 data |= 0x80 ; /* SR16 D7=1,D6=0 */ 872 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */ 873 /* XGINew_Delay15us( 0x100 ) ; */ 874} 875 876 877/* --------------------------------------------------------------------- */ 878/* Function : XGINew_DDR1x_MRS_340 */ 879/* Input : */ 880/* Output : */ 881/* Description : */ 882/* --------------------------------------------------------------------- */ 883void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 884 PVB_DEVICE_INFO pVBInfo) 885{ 886 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ; 887 if ( HwDeviceExtension->jChipType == XG42 ) /* XG42 BA0 & BA1 layout change */ 888 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 889 else 890 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 891 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 892 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 893 894 /* Samsung F Die */ 895 if (pVBInfo->DRAMTypeDefinition != 0x0C) { 896 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */ 897 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 898 if ( HwDeviceExtension->jChipType == XG42 ) 899 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 900 else 901 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 902 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 903 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 904 } 905 906 DelayUS( 60 ) ; 907 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 908 909 if (HwDeviceExtension->jChipType == XG45) 910 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ; /*TSop DRAM DLL pin jump to A9*/ 911 else 912 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/ 913 914 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ; 915 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ; 916 DelayUS( 1000 ) ; 917 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 918 DelayUS( 500 ) ; 919 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 920 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 921 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ; 922 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ; 923 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 924} 925 926 927/* --------------------------------------------------------------------- */ 928/* Function : XGINew_DDR2x_MRS_340 */ 929/* Input : */ 930/* Output : */ 931/* Description : */ 932/* --------------------------------------------------------------------- */ 933void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 934 PVB_DEVICE_INFO pVBInfo) 935{ 936 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 937 if ( HwDeviceExtension->jChipType == XG42 ) /*XG42 BA0 & BA1 layout change*/ 938 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 939 else 940 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 941 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 942 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 943 944 /* Samsung F Die */ 945 if (pVBInfo->DRAMTypeDefinition != 0x0C) { 946 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */ 947 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 948 if ( HwDeviceExtension->jChipType == XG42 ) 949 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 950 else 951 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 952 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 953 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 954 } 955 956 DelayUS( 60 ) ; 957 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 958 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 959 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/ 960 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ; 961 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ; 962 DelayUS( 1000 ) ; 963 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 964 DelayUS( 500 ) ; 965 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 966 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 967 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 968 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ; 969 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ; 970 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 971} 972 973 974/* --------------------------------------------------------------------- */ 975/* Function : XGINew_DDR2_MRS_340 */ 976/* Input : */ 977/* Output : */ 978/* Description : */ 979/* --------------------------------------------------------------------- */ 980void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 981 PVB_DEVICE_INFO pVBInfo) 982{ 983 USHORT P3d4 = P3c4 + 0x10 ; 984 UCHAR data ; 985 986 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , 0x64 ) ; /* SR28 */ 987 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , 0x63 ) ; /* SR29 */ 988 DelayUS( 200 ) ; 989 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 990 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 991 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 992 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 993 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ; 994 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ; 995 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 996 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 997 DelayUS( 2 ) ; 998 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 999 1000 if( P3c4 != pVBInfo->P3c4 ) 1001 { 1002 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 ) ; 1003 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , data ) ; /* SR28 */ 1004 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 ) ; 1005 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , data ) ; /* SR29 */ 1006 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A ) ; 1007 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2A , data ) ; /* SR2A */ 1008 1009 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E ) ; 1010 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2e , data ) ; /* SR2E */ 1011 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F ) ; 1012 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2f , data ) ; /* SR2F */ 1013 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 ) ; 1014 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x30 , data ) ; /* SR30 */ 1015 } 1016 else 1017 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1018 1019 DelayUS( 1000 ) ; 1020 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ; 1021 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ; 1022 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1023 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1024 DelayUS( 1 ) ; 1025 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1026 DelayUS( 5) ; 1027 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1028 DelayUS( 5 ) ; 1029 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x72 ) ; */ 1030 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 1031 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ; 1032 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1033 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1034 DelayUS( 1 ) ; 1035} 1036 1037/* --------------------------------------------------------------------- */ 1038/* Function : XGINew_DDRII_Bootup_XG27 */ 1039/* Input : */ 1040/* Output : */ 1041/* Description : */ 1042/* --------------------------------------------------------------------- */ 1043void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1044{ 1045 USHORT P3d4 = P3c4 + 0x10 ; 1046 UCHAR data ; 1047 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1048 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1049 1050 /* Set Double Frequency */ 1051 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */ 1052 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , pVBInfo->CR97 ) ; /* CR97 */ 1053 1054 DelayUS( 200 ) ; 1055 1056 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS2*/ 1057 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */ 1058 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1059 DelayUS( 15 ) ; 1060 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1061 DelayUS( 15 ) ; 1062 1063 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS3*/ 1064 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */ 1065 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1066 DelayUS( 15 ) ; 1067 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1068 DelayUS( 15) ; 1069 1070 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS1*/ 1071 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 1072 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1073 DelayUS( 30 ) ; 1074 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1075 DelayUS( 15 ) ; 1076 1077 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Enable*/ 1078 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */ 1079 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1080 DelayUS( 30 ) ; 1081 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1082 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */ 1083 /* DelayUS( 15 ) ; */ 1084 1085 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */ 1086 DelayUS( 60 ) ; 1087 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */ 1088 1089 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Reset*/ 1090 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */ 1091 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1092 1093 DelayUS( 30 ) ; 1094 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */ 1095 DelayUS( 15 ) ; 1096 1097 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ /*MRS, ODT*/ 1098 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */ 1099 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1100 DelayUS( 30 ) ; 1101 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1102 DelayUS( 15 ) ; 1103 1104 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS*/ 1105 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 1106 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1107 DelayUS( 30 ) ; 1108 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1109 DelayUS( 15 ) ; 1110 1111 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */ 1112 DelayUS( 200 ) ; 1113} 1114/* --------------------------------------------------------------------- */ 1115/* Function : XGINew_DDR2_MRS_XG20 */ 1116/* Input : */ 1117/* Output : */ 1118/* Description : */ 1119/* --------------------------------------------------------------------- */ 1120void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1121{ 1122 USHORT P3d4 = P3c4 + 0x10 ; 1123 UCHAR data ; 1124 1125 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1126 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1127 1128 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 1129 1130 DelayUS( 200 ) ; 1131 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 1132 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; 1133 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1134 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1135 1136 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 1137 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; 1138 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1139 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1140 1141 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 1142 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 1143 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1144 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1145 1146 /* XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS1 */ 1147 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1148 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; 1149 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1150 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1151 1152 DelayUS( 15 ) ; 1153 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1154 DelayUS( 30 ) ; 1155 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1156 DelayUS( 100 ) ; 1157 1158 /*XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS2 */ 1159 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1160 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 1161 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1162 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1163 1164 DelayUS( 200 ) ; 1165} 1166 1167/* --------------------------------------------------------------------- */ 1168/* Function : XGINew_DDR2_MRS_XG27 */ 1169/* Input : */ 1170/* Output : */ 1171/* Description : */ 1172/* --------------------------------------------------------------------- */ 1173void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1174{ 1175 USHORT P3d4 = P3c4 + 0x10 ; 1176 UCHAR data ; 1177 1178 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1179 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1180 1181 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 1182 DelayUS( 200 ) ; 1183 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 1184 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; 1185 1186 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x10 ) ; 1187 DelayUS( 15 ) ; /* 06/11/23 XG27 A0 for CKE enable*/ 1188 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x90 ) ; 1189 1190 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 1191 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; 1192 1193 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1194 DelayUS( 15 ) ; /*06/11/22 XG27 A0*/ 1195 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1196 1197 1198 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 1199 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 1200 1201 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1202 DelayUS( 15 ) ; /*06/11/22 XG27 A0 */ 1203 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1204 1205 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1206 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ; /*[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM*/ 1207 1208 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1209 DelayUS( 15 ) ; /*06/11/23 XG27 A0*/ 1210 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1211 1212 DelayUS( 30 ) ; /*06/11/23 XG27 A0 Start Auto-PreCharge*/ 1213 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1214 DelayUS( 60 ) ; 1215 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1216 1217 1218 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1219 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x04 ) ; /* DLL without Reset for XG27 Hynix DRAM*/ 1220 1221 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1222 DelayUS( 30 ) ; 1223 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1224 1225 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ); /*XG27 OCD ON */ 1226 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 ); 1227 1228 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1229 DelayUS( 30 ) ; 1230 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1231 1232 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ); 1233 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ); 1234 1235 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1236 DelayUS( 30 ) ; 1237 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1238 1239 DelayUS( 15 ) ; /*Start Auto-PreCharge*/ 1240 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1241 DelayUS( 200 ) ; 1242 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; /* SR1B */ 1243} 1244 1245 1246/* --------------------------------------------------------------------- */ 1247/* Function : XGINew_DDR1x_DefaultRegister */ 1248/* Input : */ 1249/* Output : */ 1250/* Description : */ 1251/* --------------------------------------------------------------------- */ 1252void XGINew_DDR1x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1253 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1254{ 1255 USHORT P3d4 = Port , 1256 P3c4 = Port - 0x10 ; 1257#ifndef LINUX_XF86 1258 UCHAR data ; 1259#endif 1260 if ( HwDeviceExtension->jChipType >= XG20 ) 1261 { 1262 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1263 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1264 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1265 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1266 1267 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1268 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1269 1270 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ; 1271 } 1272 else 1273 { 1274 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1275 1276 switch( HwDeviceExtension->jChipType ) 1277 { 1278 case XG41: 1279 case XG42: 1280 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1281 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1282 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1283 break ; 1284 default: 1285 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ; 1286 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1287 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1288 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1289 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; 1290 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; 1291 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1292 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1293 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1294 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1295 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1296 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1297 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1298 break ; 1299 } 1300 if (HwDeviceExtension->jChipType != XG45) 1301 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x00 ) ; 1302 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1303 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1304 XGINew_DDR1x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ; 1305 } 1306} 1307 1308 1309/* --------------------------------------------------------------------- */ 1310/* Function : XGINew_DDR2x_DefaultRegister */ 1311/* Input : */ 1312/* Output : */ 1313/* Description : */ 1314/* --------------------------------------------------------------------- */ 1315void XGINew_DDR2x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1316 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1317{ 1318 USHORT P3d4 = Port , 1319 P3c4 = Port - 0x10 ; 1320 1321#ifndef LINUX_XF86 1322 UCHAR data ; 1323#endif 1324 1325 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1326 1327 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */ 1328 switch( HwDeviceExtension->jChipType ) 1329 { 1330 case XG41: 1331 case XG42: 1332 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1333 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1334 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1335 break ; 1336 default: 1337 /* keep following setting sequence, each setting in the same reg insert idle */ 1338 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ; 1339 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1340 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1341 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1342 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1343 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1344 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1345 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1346 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1347 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1348 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1349 } 1350 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; 1351 if ( HwDeviceExtension->jChipType == XG42 ) 1352 { 1353 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1354 } 1355 else 1356 { 1357 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ; 1358 } 1359 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1360 1361 XGINew_DDR2x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ; 1362} 1363 1364 1365/* --------------------------------------------------------------------- */ 1366/* Function : XGINew_DDR2_DefaultRegister */ 1367/* Input : */ 1368/* Output : */ 1369/* Description : */ 1370/* --------------------------------------------------------------------- */ 1371void XGINew_DDR2_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1372 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1373{ 1374 USHORT P3d4 = Port , 1375 P3c4 = Port - 0x10 ; 1376 1377 /* keep following setting sequence, each setting in the same reg insert idle */ 1378 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1379 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1380 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1381 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1382 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1383 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1384 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1385 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1386 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1387 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1388 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1389 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1390 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1391 1392 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ; 1393 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1394 1395 /* Jong 10/01/2007 */ 1396 if ( HwDeviceExtension->jChipType == XG27 ) 1397 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ; 1398 else if ( HwDeviceExtension->jChipType >= XG20 ) 1399 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ; 1400 else 1401 XGINew_DDR2_MRS_340( HwDeviceExtension , P3c4, pVBInfo ) ; 1402} 1403 1404 1405/* --------------------------------------------------------------------- */ 1406/* Function : XGINew_SetDRAMDefaultRegister340 */ 1407/* Input : */ 1408/* Output : */ 1409/* Description : */ 1410/* --------------------------------------------------------------------- */ 1411void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo) 1412{ 1413 UCHAR temp , temp1 , temp2 , temp3 , 1414 i , j , k ; 1415 1416 USHORT P3d4 = Port , 1417 P3c4 = Port - 0x10 ; 1418 1419 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ; 1420 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ; 1421 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ; 1422 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ; 1423 1424 temp2 = 0 ; 1425 for( i = 0 ; i < 4 ; i++ ) 1426 { 1427 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */ 1428 for( j = 0 ; j < 4 ; j++ ) 1429 { 1430 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1431 temp2 |= temp1 ; 1432 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp2 ) ; 1433 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6B ) ; /* Insert read command for delay */ 1434 temp2 &= 0xF0 ; 1435 temp2 += 0x10 ; 1436 } 1437 } 1438 1439 temp2 = 0 ; 1440 for( i = 0 ; i < 4 ; i++ ) 1441 { 1442 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */ 1443 for( j = 0 ; j < 4 ; j++ ) 1444 { 1445 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1446 temp2 |= temp1 ; 1447 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , temp2 ) ; 1448 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6E ) ; /* Insert read command for delay */ 1449 temp2 &= 0xF0 ; 1450 temp2 += 0x10 ; 1451 } 1452 } 1453 1454 temp3 = 0 ; 1455 for( k = 0 ; k < 4 ; k++ ) 1456 { 1457 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */ 1458 temp2 = 0 ; 1459 for( i = 0 ; i < 8 ; i++ ) 1460 { 1461 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */ 1462 for( j = 0 ; j < 4 ; j++ ) 1463 { 1464 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1465 temp2 |= temp1 ; 1466 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , temp2 ) ; 1467 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6F ) ; /* Insert read command for delay */ 1468 temp2 &= 0xF8 ; 1469 temp2 += 0x08 ; 1470 } 1471 } 1472 temp3 += 0x01 ; 1473 } 1474 1475 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */ 1476 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */ 1477 1478 temp2 = 0x80 ; 1479 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */ 1480 for( j = 0 ; j < 4 ; j++ ) 1481 { 1482 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1483 temp2 |= temp1 ; 1484 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1485 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */ 1486 temp2 &= 0xF0 ; 1487 temp2 += 0x10 ; 1488 } 1489 1490 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ; 1491 temp1 = temp & 0x03 ; 1492 temp2 |= temp1 ; 1493 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1494 1495 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ; 1496 temp1 = temp & 0x0F ; 1497 temp2 = ( temp >> 4 ) & 0x07 ; 1498 temp3 = temp & 0x80 ; 1499 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , temp1 ) ; /* CR45 */ 1500 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , temp2 ) ; /* CR99 */ 1501 XGI_SetRegOR((XGIIOADDRESS) P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */ 1502 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */ 1503 1504 /* Jong 10/01/2007; */ 1505 if ( HwDeviceExtension->jChipType == XG27 ) 1506 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */ 1507 1508 for( j = 0 ; j <= 6 ; j++ ) 1509 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */ 1510 1511 for( j = 0 ; j <= 2 ; j++ ) 1512 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */ 1513 1514 for( j = 0 ; j < 2 ; j++ ) 1515 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */ 1516 1517 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) ) 1518 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ; 1519 1520 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */ 1521 1522 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */ 1523 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */ 1524 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */ 1525 1526 /* Jong 10/01/2007 */ 1527 if ( XGINew_RAMType ) 1528 { 1529 /*XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0xC0 ) ;*/ /* SR17 DDRII */ 1530 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */ 1531 if ( HwDeviceExtension->jChipType == XG27 ) 1532 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */ 1533 1534 } 1535 else 1536 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */ 1537 1538 XGI_SetReg((XGIIOADDRESS) P3c4, 0x1A, 0x87); /* SR1A */ 1539 1540 temp = XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) ; 1541 if( temp == 0 ) 1542 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1543 else if ( temp == 0x02 ) 1544 XGINew_DDR2x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1545 else 1546 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1547 1548 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1549} 1550 1551/* --------------------------------------------------------------------- */ 1552/* Function : XGINew_SetDRAMDefaultRegisterXG45 */ 1553/* Input : */ 1554/* Output : */ 1555/* Description : */ 1556/* --------------------------------------------------------------------- */ 1557void XGINew_SetDRAMDefaultRegisterXG45( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo) 1558{ 1559 UCHAR temp , temp1 , temp2 , 1560 i , j , k ; 1561 1562 USHORT P3d4 = Port , 1563 P3c4 = Port - 0x10 ; 1564 1565 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ; 1566 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , pVBInfo->XG45CR6E[ XGINew_RAMType ] ) ; 1567 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , pVBInfo->XG45CR6F[ XGINew_RAMType ] ) ; 1568 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ; 1569 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ; 1570 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ; 1571 1572 temp = 0x00 ; 1573 for ( j = 0 ; j < 24 ; j ++ ) 1574 { 1575 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp ); 1576 temp += 0x08 ; 1577 } 1578 1579 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */ 1580 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */ 1581 1582 temp2 = 0x80 ; 1583 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */ 1584 for( j = 0 ; j < 4 ; j++ ) 1585 { 1586 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1587 temp2 |= temp1 ; 1588 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1589 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */ 1590 temp2 &= 0xF0 ; 1591 temp2 += 0x10 ; 1592 } 1593 1594 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ; 1595 temp1 = temp & 0x03 ; 1596 temp2 |= temp1 ; 1597 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1598 1599 temp = 0x00 ; 1600 for ( j = 0 ; j < 3 ; j ++ ) 1601 { 1602 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x40 , temp ); 1603 temp += 0x40 ; 1604 } 1605 1606 temp = 0x00 ; 1607 for ( j = 0 ; j < 24 ; j ++ ) 1608 { 1609 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , temp ); 1610 temp += 0x08 ; 1611 } 1612 1613 temp = 0x00 ; 1614 for ( j = 0 ; j < 24 ; j ++ ) 1615 { 1616 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x42 , temp ); 1617 temp += 0x08 ; 1618 } 1619 1620 for ( k = 0 ; k < 2 ; k ++ ) 1621 { 1622 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x04 , k * 0x04 ); 1623 1624 for ( i = 0 ; i < 3 ; i ++ ) 1625 { 1626 1627 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x03 , i * 0x01 ); 1628 1629 for ( j = 0 ; j < 32 ; j ++ ) 1630 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x44 , j * 0x08 ); 1631 } 1632 } 1633 1634 for ( j = 0 ; j < 3 ; j ++ ) 1635 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , j * 0x08 ) ; /* CR45 */ 1636 1637 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x84 ) ; 1638 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1639 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , 0x22 ) ; 1640 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1641 1642 for( j = 0 ; j <= 6 ; j++ ) 1643 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */ 1644 1645 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */ 1646 1647 for( j = 0 ; j <= 2 ; j++ ) 1648 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */ 1649 1650 XGI_SetReg((XGIIOADDRESS) P3d4 , 0xC8 , 0x04 ) ; 1651 1652 for( j = 0 ; j < 2 ; j++ ) 1653 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */ 1654 1655 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x40 ) ; 1656 1657 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) ) 1658 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ; 1659 1660 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */ 1661 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */ 1662 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */ 1663 XGI_SetReg((XGIIOADDRESS) P3d4, 0x8D, 0x87); /* CR8D */ 1664 1665 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1666 1667 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1A , 0x87 ) ; /* SR1A */ 1668 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1669} 1670 1671/* --------------------------------------------------------------------- */ 1672/* Function : XGINew_DDR_MRS */ 1673/* Input : */ 1674/* Output : */ 1675/* Description : */ 1676/* --------------------------------------------------------------------- */ 1677void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo) 1678{ 1679 USHORT data ; 1680 1681 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 1682 1683 /* SR16 <- 1F,DF,2F,AF */ 1684 /* yriver modified SR16 <- 0F,DF,0F,AF */ 1685 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */ 1686 data = pVideoMemory[ 0xFB ] ; 1687 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ; */ 1688 1689 data &= 0x0F ; 1690 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1691 data |= 0xC0 ; 1692 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1693 data &= 0x0F ; 1694 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1695 data |= 0x80 ; 1696 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1697 data &= 0x0F ; 1698 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1699 data |= 0xD0 ; 1700 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1701 data &= 0x0F ; 1702 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1703 data |= 0xA0 ; 1704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1705/* 1706 else { 1707 data &= 0x0F; 1708 data |= 0x10; 1709 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1710 1711 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1712 { 1713 data &= 0x0F; 1714 } 1715 1716 data |= 0xC0; 1717 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1718 1719 1720 data &= 0x0F; 1721 data |= 0x20; 1722 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1723 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1724 { 1725 data &= 0x0F; 1726 } 1727 1728 data |= 0x80; 1729 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1730 } 1731*/ 1732} 1733 1734 1735/* --------------------------------------------------------------------- */ 1736/* Function : XGINew_SetDRAMSize_340 */ 1737/* Input : */ 1738/* Output : */ 1739/* Description : */ 1740/* --------------------------------------------------------------------- */ 1741void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1742{ 1743 USHORT data ; 1744 1745 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1746 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1747 XGISetModeNew(HwDeviceExtension, pVBInfo, 0x2e); 1748 1749 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1750 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */ 1751 1752 /* Jong 10/03/2007; add support for DVO, XG27, ...*/ 1753 XGI_DisplayOff(HwDeviceExtension, pVBInfo ); 1754 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ; 1755 data |= 0x20 ; 1756 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; */ /* Turn OFF Display */ 1757 1758 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ; 1759 1760 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1761 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */ 1762} 1763 1764 1765/*--------------------------------------------------------------------- */ 1766/* Function : XGINew_SetDRAMSize_XG45 */ 1767/*Input : */ 1768/*Output : */ 1769/*Description : */ 1770/*--------------------------------------------------------------------- */ 1771void XGINew_SetDRAMSize_XG45( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1772{ 1773 USHORT data ; 1774 1775 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1776 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1777 XGISetModeNew(HwDeviceExtension, pVBInfo, 0x2e); 1778 1779 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1780 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /*disable read cache*/ 1781 1782 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ; 1783 data |= 0x20 ; 1784 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; /*Turn OFF Display*/ 1785 1786 XGINew_DDRSizingXG45( HwDeviceExtension, pVBInfo ) ; 1787 1788 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1789 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /*enable read cache*/ 1790} 1791 1792 1793/* --------------------------------------------------------------------- */ 1794/* Function : XGINew_SetDRAMModeRegister340 */ 1795/* Input : */ 1796/* Output : */ 1797/* Description : */ 1798/* --------------------------------------------------------------------- */ 1799 1800void XGINew_SetDRAMModeRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1801 PVB_DEVICE_INFO pVBInfo) 1802{ 1803 UCHAR data ; 1804 1805 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 1806 1807 if (HwDeviceExtension->jChipType == XG45) 1808 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1809 else 1810 { 1811 if ( XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 1812 { 1813 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ; 1814 if ( data == 0x01 ) 1815 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1816 else 1817 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1818 } 1819 else 1820 XGINew_DDR2_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo); 1821 } 1822 1823 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ; 1824} 1825 1826 1827/* --------------------------------------------------------------------- */ 1828/* Function : XGINew_DisableRefresh */ 1829/* Input : */ 1830/* Output : */ 1831/* Description : */ 1832/* --------------------------------------------------------------------- */ 1833void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1834{ 1835 USHORT data ; 1836 1837 1838 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B ) ; 1839 data &= 0xF8 ; 1840 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , data ) ; 1841 1842} 1843 1844 1845/* --------------------------------------------------------------------- */ 1846/* Function : XGINew_EnableRefresh */ 1847/* Input : */ 1848/* Output : */ 1849/* Description : */ 1850/* --------------------------------------------------------------------- */ 1851void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1852{ 1853 1854 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1855 1856 1857} 1858 1859 1860/* --------------------------------------------------------------------- */ 1861/* Function : XGINew_DisableChannelInterleaving */ 1862/* Input : */ 1863/* Output : */ 1864/* Description : */ 1865/* --------------------------------------------------------------------- */ 1866void XGINew_DisableChannelInterleaving(int index, 1867 const USHORT XGINew_DDRDRAM_TYPE[][5], 1868 PVB_DEVICE_INFO pVBInfo) 1869{ 1870 USHORT data ; 1871 1872 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ; 1873 data &= 0x1F ; 1874 1875 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] ) 1876 { 1877 case 64: 1878 data |= 0 ; 1879 break ; 1880 case 32: 1881 data |= 0x20 ; 1882 break ; 1883 case 16: 1884 data |= 0x40 ; 1885 break ; 1886 case 4: 1887 data |= 0x60 ; 1888 break ; 1889 default: 1890 break ; 1891 } 1892 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ; 1893} 1894 1895 1896/* --------------------------------------------------------------------- */ 1897/* Function : XGINew_SetDRAMSizingType */ 1898/* Input : */ 1899/* Output : */ 1900/* Description : */ 1901/* --------------------------------------------------------------------- */ 1902void XGINew_SetDRAMSizingType(int index , const USHORT DRAMTYPE_TABLE[][5], 1903 PVB_DEVICE_INFO pVBInfo) 1904{ 1905 USHORT data ; 1906 1907 data = DRAMTYPE_TABLE[ index ][ 4 ] ; 1908 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x80 , data ) ; 1909 /* should delay 50 ns */ 1910} 1911 1912 1913/* --------------------------------------------------------------------- */ 1914/* Function : XGINew_SetRank */ 1915/* Input : */ 1916/* Output : */ 1917/* Description : */ 1918/* --------------------------------------------------------------------- */ 1919int XGINew_SetRank(int index, UCHAR RankNo, UCHAR XGINew_ChannelAB, 1920 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo) 1921{ 1922 USHORT data ; 1923 int RankSize ; 1924 1925 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) ) 1926 return 0 ; 1927 1928 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ; 1929 1930 if ( ( RankNo * RankSize ) <= 128 ) 1931 { 1932 data = 0 ; 1933 1934 while( ( RankSize >>= 1 ) > 0 ) 1935 { 1936 data += 0x10 ; 1937 } 1938 data |= ( RankNo - 1 ) << 2 ; 1939 data |= ( XGINew_DataBusWidth / 64 ) & 2 ; 1940 data |= XGINew_ChannelAB ; 1941 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 1942 /* should delay */ 1943 XGINew_SDR_MRS( pVBInfo ) ; 1944 return( 1 ) ; 1945 } 1946 else 1947 return( 0 ) ; 1948} 1949 1950 1951/* --------------------------------------------------------------------- */ 1952/* Function : XGINew_SetDDRChannel */ 1953/* Input : */ 1954/* Output : */ 1955/* Description : */ 1956/* --------------------------------------------------------------------- */ 1957int XGINew_SetDDRChannel(int index, UCHAR ChannelNo, UCHAR XGINew_ChannelAB, 1958 const USHORT DRAMTYPE_TABLE[][5], 1959 PVB_DEVICE_INFO pVBInfo) 1960{ 1961 USHORT data ; 1962 int RankSize ; 1963 1964 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32; 1965 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */ 1966 if ( ChannelNo * RankSize <= 128 ) 1967 { 1968 data = 0 ; 1969 while( ( RankSize >>= 1 ) > 0 ) 1970 { 1971 data += 0x10 ; 1972 } 1973 1974 if ( ChannelNo == 2 ) 1975 data |= 0x0C ; 1976 1977 data |= ( XGINew_DataBusWidth / 32 ) & 2 ; 1978 data |= XGINew_ChannelAB ; 1979 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 1980 /* should delay */ 1981 XGINew_DDR_MRS( pVBInfo ) ; 1982 return( 1 ) ; 1983 } 1984 else 1985 return( 0 ) ; 1986} 1987 1988 1989/* --------------------------------------------------------------------- */ 1990/* Function : XGINew_CheckColumn */ 1991/* Input : */ 1992/* Output : */ 1993/* Description : */ 1994/* --------------------------------------------------------------------- */ 1995int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5], 1996 PVB_DEVICE_INFO pVBInfo) 1997{ 1998 int i ; 1999 ULONG Increment , Position ; 2000 2001 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */ 2002 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ; 2003 2004 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2005 { 2006 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2007 Position += Increment ; 2008 } 2009 2010 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2011 { 2012 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 2013 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2014 return( 0 ) ; 2015 Position += Increment ; 2016 } 2017 return( 1 ) ; 2018} 2019 2020 2021/* --------------------------------------------------------------------- */ 2022/* Function : XGINew_CheckBanks */ 2023/* Input : */ 2024/* Output : */ 2025/* Description : */ 2026/* --------------------------------------------------------------------- */ 2027int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5], 2028 PVB_DEVICE_INFO pVBInfo) 2029{ 2030 int i ; 2031 ULONG Increment , Position ; 2032 2033 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ; 2034 2035 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 2036 { 2037 /* pVBInfo->FBAddr[ Position ] = Position ; */ 2038 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2039 Position += Increment ; 2040 } 2041 2042 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 2043 { 2044 /* if (pVBInfo->FBAddr[ Position ] != Position ) */ 2045 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2046 return( 0 ) ; 2047 Position += Increment ; 2048 } 2049 return( 1 ) ; 2050} 2051 2052 2053/* --------------------------------------------------------------------- */ 2054/* Function : XGINew_CheckRank */ 2055/* Input : */ 2056/* Output : */ 2057/* Description : */ 2058/* --------------------------------------------------------------------- */ 2059int XGINew_CheckRank(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5], 2060 PVB_DEVICE_INFO pVBInfo) 2061{ 2062 int i ; 2063 ULONG Increment , Position ; 2064 2065 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 2066 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 2067 2068 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2069 { 2070 /* pVBInfo->FBAddr[ Position ] = Position ; */ 2071 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */ 2072 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2073 Position += Increment ; 2074 } 2075 2076 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2077 { 2078 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 2079 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */ 2080 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2081 return( 0 ) ; 2082 Position += Increment ; 2083 } 2084 return( 1 ); 2085} 2086 2087 2088/* --------------------------------------------------------------------- */ 2089/* Function : XGINew_CheckDDRRank */ 2090/* Input : */ 2091/* Output : */ 2092/* Description : */ 2093/* --------------------------------------------------------------------- */ 2094int XGINew_CheckDDRRank(int RankNo, int index, 2095 const USHORT DRAMTYPE_TABLE[][5], 2096 PVB_DEVICE_INFO pVBInfo) 2097{ 2098 ULONG Increment , Position ; 2099 USHORT data ; 2100 2101 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 2102 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 2103 2104 Increment += Increment / 2 ; 2105 2106 Position = 0; 2107 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ; 2108 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ; 2109 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ; 2110 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ; 2111 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ; 2112 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ; 2113 2114 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB ) 2115 return( 1 ) ; 2116 2117 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 ) 2118 return( 0 ) ; 2119 2120 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) ; 2121 data &= 0xF3 ; 2122 data |= 0x0E ; 2123 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 2124 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ; 2125 data += 0x20 ; 2126 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ; 2127 2128 return( 1 ) ; 2129} 2130 2131 2132/* --------------------------------------------------------------------- */ 2133/* Function : XGINew_CheckRanks */ 2134/* Input : */ 2135/* Output : */ 2136/* Description : */ 2137/* --------------------------------------------------------------------- */ 2138int XGINew_CheckRanks(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5], 2139 PVB_DEVICE_INFO pVBInfo) 2140{ 2141 int r ; 2142 2143 for( r = RankNo ; r >= 1 ; r-- ) 2144 { 2145 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 2146 return( 0 ) ; 2147 } 2148 2149 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 2150 return( 0 ) ; 2151 2152 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 2153 return( 0 ) ; 2154 2155 return( 1 ) ; 2156} 2157 2158 2159/* --------------------------------------------------------------------- */ 2160/* Function : XGINew_CheckDDRRanks */ 2161/* Input : */ 2162/* Output : */ 2163/* Description : */ 2164/* --------------------------------------------------------------------- */ 2165int XGINew_CheckDDRRanks(int RankNo, int index, 2166 const USHORT DRAMTYPE_TABLE[][5], 2167 PVB_DEVICE_INFO pVBInfo) 2168{ 2169 int r ; 2170 2171 for( r = RankNo ; r >= 1 ; r-- ) 2172 { 2173 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 2174 return( 0 ) ; 2175 } 2176 2177 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 2178 return( 0 ) ; 2179 2180 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 2181 return( 0 ) ; 2182 2183 return( 1 ) ; 2184} 2185 2186 2187/* --------------------------------------------------------------------- */ 2188/* Function : */ 2189/* Input : */ 2190/* Output : */ 2191/* Description : */ 2192/* --------------------------------------------------------------------- */ 2193int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo) 2194{ 2195 int i ; 2196 UCHAR j ; 2197 2198 for( i = 0 ; i < 13 ; i++ ) 2199 { 2200 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ; 2201 2202 for( j = 2 ; j > 0 ; j-- ) 2203 { 2204 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) ) 2205 continue ; 2206 else 2207 { 2208 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) ) 2209 return( 1 ) ; 2210 } 2211 } 2212 } 2213 return( 0 ) ; 2214} 2215 2216 2217/* --------------------------------------------------------------------- */ 2218/* Function : XGINew_SetDRAMSizeReg */ 2219/* Input : */ 2220/* Output : */ 2221/* Description : */ 2222/* --------------------------------------------------------------------- */ 2223USHORT XGINew_SetDRAMSizeReg(int index, const USHORT DRAMTYPE_TABLE[][5], 2224 PVB_DEVICE_INFO pVBInfo) 2225{ 2226 USHORT data = 0 , memsize = 0 ; 2227 int RankSize ; 2228 UCHAR ChannelNo ; 2229 2230 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ; 2231 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ; 2232 data &= 0x80 ; 2233 2234 if ( data == 0x80 ) 2235 RankSize *= 2 ; 2236 2237 data = 0 ; 2238 2239 if( XGINew_ChannelAB == 3 ) 2240 ChannelNo = 4 ; 2241 else 2242 ChannelNo = XGINew_ChannelAB ; 2243 2244 if ( ChannelNo * RankSize <= 256 ) 2245 { 2246 while( ( RankSize >>= 1 ) > 0 ) 2247 { 2248 data += 0x10 ; 2249 } 2250 2251 memsize = data >> 4 ; 2252 2253 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2254 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2255 2256 /* data |= XGINew_ChannelAB << 2 ; */ 2257 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2258 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; */ 2259 2260 /* should delay */ 2261 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2262 } 2263 return( memsize ) ; 2264} 2265 2266/* --------------------------------------------------------------------- */ 2267/* Function : XGINew_SetDRAMSize20Reg */ 2268/* Input : */ 2269/* Output : */ 2270/* Description : */ 2271/* --------------------------------------------------------------------- */ 2272USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo) 2273{ 2274 USHORT data = 0 , memsize = 0 ; 2275 int RankSize ; 2276 UCHAR ChannelNo ; 2277 2278 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ; 2279 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ; 2280 data &= 0x80 ; 2281 2282 if ( data == 0x80 ) 2283 RankSize *= 2 ; 2284 2285 data = 0 ; 2286 2287 if( XGINew_ChannelAB == 3 ) 2288 ChannelNo = 4 ; 2289 else 2290 ChannelNo = XGINew_ChannelAB ; 2291 2292 if ( ChannelNo * RankSize <= 256 ) 2293 { 2294 while( ( RankSize >>= 1 ) > 0 ) 2295 { 2296 data += 0x10 ; 2297 } 2298 2299 memsize = data >> 4 ; 2300 2301 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2302 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2303 DelayUS( 15 ) ; 2304 2305 /* data |= XGINew_ChannelAB << 2 ; */ 2306 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2307 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */ 2308 2309 /* should delay */ 2310 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2311 } 2312 return( memsize ) ; 2313} 2314 2315 2316/* --------------------------------------------------------------------- */ 2317/* Function : XGINew_ReadWriteRest */ 2318/* Input : */ 2319/* Output : */ 2320/* Description : */ 2321/* --------------------------------------------------------------------- */ 2322int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr, 2323 PVB_DEVICE_INFO pVBInfo) 2324{ 2325 int i ; 2326 ULONG Position = 0 ; 2327 2328 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2329 2330 for( i = StartAddr ; i <= StopAddr ; i++ ) 2331 { 2332 Position = 1 << i ; 2333 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2334 } 2335 2336 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 2337 2338 Position = 0 ; 2339 2340 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2341 return( 0 ) ; 2342 2343 for( i = StartAddr ; i <= StopAddr ; i++ ) 2344 { 2345 Position = 1 << i ; 2346 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2347 return( 0 ) ; 2348 } 2349 return( 1 ) ; 2350} 2351 2352 2353/*--------------------------------------------------------------------- */ 2354/* Function : XGI45New_ReadWriteRest */ 2355/* Input : */ 2356/* Output : */ 2357/* Description : return 0 : fail, 1 : pass */ 2358/*--------------------------------------------------------------------- */ 2359int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr, 2360 PVB_DEVICE_INFO pVBInfo) 2361{ 2362 int i ; 2363 ULONG Position = 0 ; 2364 2365 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2366 2367 for( i = StartAddr ; i <= StopAddr ; i++ ) 2368 { 2369 Position = 1 << i ; 2370 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2371 } 2372 2373 if ( XGINew_ChannelAB == 4 ) 2374 { 2375 Position = ( 1 << StopAddr ) + ( 1 << ( StopAddr - 1 ) ); 2376 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2377 } 2378 2379 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 2380 2381 Position = 0 ; 2382 2383 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2384 return( 0 ) ; 2385 2386 for( i = StartAddr ; i <= StopAddr ; i++ ) 2387 { 2388 Position = 1 << i ; 2389 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2390 return( 0 ) ; 2391 } 2392 2393 if ( XGINew_ChannelAB == 4 ) 2394 { 2395 Position = ( 1 << StopAddr ) + ( 1 << ( StopAddr - 1 ) ); 2396 if( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ); 2397 return( 0 ) ; 2398 } 2399 return( 1 ) ; 2400} 2401 2402 2403/* --------------------------------------------------------------------- */ 2404/* Function : XGINew_CheckFrequence */ 2405/* Input : */ 2406/* Output : */ 2407/* Description : */ 2408/* --------------------------------------------------------------------- */ 2409UCHAR XGINew_CheckFrequence(PVB_DEVICE_INFO pVBInfo) 2410{ 2411 UCHAR data ; 2412 2413 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 2414 2415 if ( ( data & 0x10 ) == 0 ) 2416 { 2417 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) ; 2418 data = ( data & 0x02 ) >> 1 ; 2419 return( data ) ; 2420 } 2421 else 2422 return( data & 0x01 ) ; 2423} 2424 2425 2426/* --------------------------------------------------------------------- */ 2427/* Function : XGINew_CheckChannel */ 2428/* Input : */ 2429/* Output : */ 2430/* Description : */ 2431/* --------------------------------------------------------------------- */ 2432void XGINew_CheckChannel(PXGI_HW_DEVICE_INFO HwDeviceExtension, 2433 PVB_DEVICE_INFO pVBInfo) 2434{ 2435 UCHAR i, data ; 2436 2437 switch( HwDeviceExtension->jChipType ) 2438 { 2439 case XG20: 2440 case XG21: 2441 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 2442 data = data & 0x01; 2443 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */ 2444 2445 if ( data == 0 ) /* Single_32_16 */ 2446 { 2447 /* Jong 10/03/2007 */ 2448 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000) 2449 { 2450 2451 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2452 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */ 2453 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2454 DelayUS( 15 ) ; 2455 2456 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2457 return ; 2458 2459 /* Jong 10/03/2007 */ 2460 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2461 { 2462 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */ 2463 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2464 DelayUS( 15 ) ; 2465 2466 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 ) 2467 return ; 2468 } 2469 } 2470 2471 /* Jong 10/03/2007 */ 2472 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2473 { 2474 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2475 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */ 2476 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ; 2477 DelayUS( 15 ) ; 2478 2479 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2480 return ; 2481 else 2482 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2483 2484 DelayUS( 15 ) ; 2485 } 2486 } 2487 else /* Dual_16_8 */ 2488 { 2489 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2490 { 2491 2492 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2493 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; 2494 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ; 2495 DelayUS( 15 ) ; 2496 2497 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2498 return ; 2499 2500 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2501 { 2502 2503 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2504 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x31 ) ; 2505 DelayUS( 15 ) ; 2506 2507 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 ) 2508 return ; 2509 } 2510 } 2511 2512 2513 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2514 { 2515 XGINew_DataBusWidth = 8 ; /* 8 bits */ 2516 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; 2517 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ; 2518 DelayUS( 15 ) ; 2519 2520 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 ) 2521 return ; 2522 else 2523 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2524 DelayUS( 15 ) ; 2525 } 2526 } 2527 break ; 2528 2529 case XG27: 2530 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2531 XGINew_ChannelAB = 1 ; /* Single channel */ 2532 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/ 2533 break ; 2534 2535 case XG41: 2536 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) 2537 { 2538 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2539 XGINew_ChannelAB = 3 ; /* Quad Channel */ 2540 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2541 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2542 2543 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2544 return ; 2545 2546 XGINew_ChannelAB = 2 ; /* Dual channels */ 2547 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2548 2549 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2550 return ; 2551 2552 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x49 ) ; 2553 2554 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2555 return ; 2556 2557 XGINew_ChannelAB = 3 ; 2558 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2559 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2560 2561 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2562 return ; 2563 2564 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2565 2566 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2567 return ; 2568 else 2569 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x39 ) ; 2570 } 2571 else 2572 { /* DDR */ 2573 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2574 XGINew_ChannelAB = 2 ; /* Dual channels */ 2575 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2576 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2577 2578 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2579 return ; 2580 2581 XGINew_ChannelAB = 1 ; /* Single channels */ 2582 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2583 2584 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2585 return ; 2586 2587 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x53 ) ; 2588 2589 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2590 return ; 2591 2592 XGINew_ChannelAB = 2 ; /* Dual channels */ 2593 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2594 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2595 2596 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2597 return ; 2598 2599 XGINew_ChannelAB = 1 ; /* Single channels */ 2600 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2601 2602 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2603 return ; 2604 else 2605 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x43 ) ; 2606 } 2607 2608 break ; 2609 2610 case XG42: 2611/* 2612 XG42 SR14 D[3] Reserve 2613 D[2] = 1, Dual Channel 2614 = 0, Single Channel 2615 2616 It's Different from Other XG40 Series. 2617*/ 2618 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */ 2619 { 2620 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2621 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2622 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2623 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x44 ) ; 2624 2625 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2626 return ; 2627 2628 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2629 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x34 ) ; 2630 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2631 return ; 2632 2633 XGINew_ChannelAB = 1 ; /* Single Channel */ 2634 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2635 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x40 ) ; 2636 2637 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2638 return ; 2639 else 2640 { 2641 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2642 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ; 2643 } 2644 } 2645 else 2646 { /* DDR */ 2647 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2648 XGINew_ChannelAB = 1 ; /* 1 channels */ 2649 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2650 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2651 2652 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2653 return ; 2654 else 2655 { 2656 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2657 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2658 } 2659 } 2660 2661 break ; 2662 2663 case XG45: 2664 2665 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2666 XGINew_ChannelAB = 4 ; /* 3+1 Channel */ 2667 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2668 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2669 2670 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2671 return ; 2672 2673 XGINew_ChannelAB = 3 ; /* 3 Channel */ 2674 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2675 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ; 2676 2677 if ( XGI45New_ReadWriteRest( 26 , 24 , pVBInfo ) == 1 ) 2678 return ; 2679 2680 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2681 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2682 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ; 2683 2684 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2685 return ; 2686 2687 XGINew_ChannelAB = 1 ; /* 1 Channel */ 2688 for ( i = 0; i <= 2; i++) 2689 { 2690 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2691 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ; 2692 2693 if ( XGI45New_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2694 return ; 2695 } 2696 2697 XGINew_ChannelAB = 3 ; /* 3 Channel */ 2698 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2699 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ; 2700 2701 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2702 return ; 2703 2704 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2706 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ; 2707 2708 if ( XGI45New_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2709 return ; 2710 2711 XGINew_ChannelAB = 1 ; /* 1 Channel */ 2712 for ( i = 0; i <= 2; i++) 2713 { 2714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2715 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ; 2716 2717 if ( XGI45New_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2718 return ; 2719 } 2720 break ; 2721 2722 default: /* XG40 */ 2723 2724 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */ 2725 { 2726 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2727 XGINew_ChannelAB = 3 ; 2728 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2729 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2730 2731 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2732 return ; 2733 2734 XGINew_ChannelAB = 2 ; /* 2 channels */ 2735 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2736 2737 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2738 return ; 2739 2740 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2741 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2742 2743 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2744 XGINew_ChannelAB = 3 ; /* 4 channels */ 2745 else 2746 { 2747 XGINew_ChannelAB = 2 ; /* 2 channels */ 2748 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2749 } 2750 } 2751 else 2752 { /* DDR */ 2753 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2754 XGINew_ChannelAB = 2 ; /* 2 channels */ 2755 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2756 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2757 2758 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2759 return ; 2760 else 2761 { 2762 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2763 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2764 } 2765 } 2766 break ; 2767 } 2768} 2769 2770 2771/* --------------------------------------------------------------------- */ 2772/* Function : XGINew_DDRSizing340 */ 2773/* Input : */ 2774/* Output : */ 2775/* Description : */ 2776/* --------------------------------------------------------------------- */ 2777int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2778{ 2779 int i ; 2780 USHORT memsize , addr ; 2781 2782 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */ 2783 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */ 2784 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ; 2785 2786 /* Jong 10/03/2007 */ 2787 if ( HwDeviceExtension->jChipType >= XG20 ) 2788 { 2789 for( i = 0 ; i < 12 ; i++ ) 2790 { 2791 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2792 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2793 if ( memsize == 0 ) 2794 continue ; 2795 2796 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2797 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2798 continue ; 2799 2800 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 ) 2801 return( 1 ) ; 2802 } 2803 } 2804 else 2805 { 2806 for( i = 0 ; i < 4 ; i++ ) 2807 { 2808 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2809 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2810 if ( memsize == 0 ) 2811 continue ; 2812 2813 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2814 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2815 continue ; 2816 2817 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 ) 2818 return( 1 ) ; 2819 } 2820 } 2821 return( 0 ) ; 2822} 2823 2824 2825/*--------------------------------------------------------------------- */ 2826/* Function : XGINew_DDRSizingXG45 */ 2827/* Input : */ 2828/* Output : */ 2829/* Description : */ 2830/*--------------------------------------------------------------------- */ 2831int XGINew_DDRSizingXG45( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2832{ 2833 int i ; 2834 USHORT memsize , addr ; 2835 2836 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */ 2837 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */ 2838 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ; 2839 2840 for( i = 0 ; i < 4 ; i++ ) 2841 { 2842 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2843 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2844 if ( memsize == 0 ) 2845 continue ; 2846 2847 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2848 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2849 continue ; 2850 2851 if ( XGI45New_ReadWriteRest( addr , 9, pVBInfo ) == 1 ) 2852 return( 1 ) ; 2853 } 2854 return( 0 ) ; 2855} 2856 2857 2858/* --------------------------------------------------------------------- */ 2859/* Function : XGINew_DDRSizing */ 2860/* Input : */ 2861/* Output : */ 2862/* Description : */ 2863/* --------------------------------------------------------------------- */ 2864int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo) 2865{ 2866 int i ; 2867 UCHAR j ; 2868 2869 for( i = 0 ; i < 4 ; i++ ) 2870 { 2871 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ; 2872 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ; 2873 for( j = 2 ; j > 0 ; j-- ) 2874 { 2875 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ; 2876 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) ) 2877 continue ; 2878 else 2879 { 2880 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) ) 2881 return( 1 ) ; 2882 } 2883 } 2884 } 2885 return( 0 ) ; 2886} 2887 2888/* --------------------------------------------------------------------- */ 2889/* Function : XGINew_SetMemoryClock */ 2890/* Input : */ 2891/* Output : */ 2892/* Description : */ 2893/* --------------------------------------------------------------------- */ 2894void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2895{ 2896#ifndef LINUX_XF86 2897 UCHAR tempal ; 2898#endif 2899 2900 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ; 2901 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ; 2902 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ; 2903 2904 2905 2906 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ; 2907 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ; 2908 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ; 2909 2910 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */ 2911 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */ 2912 if ( HwDeviceExtension->jChipType == XG42 ) 2913 { 2914 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 ) 2915 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) 2916 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) ) 2917 { 2918 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ; 2919 } 2920 } 2921} 2922 2923 2924/* --------------------------------------------------------------------- */ 2925/* input : dx ,valid value : CR or second chip's CR */ 2926/* */ 2927/* SetPowerConsume : */ 2928/* Description: reduce 40/43 power consumption in first chip or */ 2929/* in second chip, assume CR A1 D[6]="1" in this case */ 2930/* output : none */ 2931/* --------------------------------------------------------------------- */ 2932void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT XGI_P3d4Port ) 2933{ 2934 ULONG lTemp ; 2935 UCHAR bTemp; 2936 2937 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */ 2938 if ((lTemp&0xFF)==0) 2939 { 2940 /* set CR58 D[5]=0 D[3]=0 */ 2941 XGI_SetRegAND((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 ) ; 2942 bTemp = (UCHAR) XGI_GetReg((XGIIOADDRESS) XGI_P3d4Port , 0xCB ) ; 2943 if (bTemp&0x20) 2944 { 2945 if (!(bTemp&0x10)) 2946 { 2947 XGI_SetRegANDOR((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */ 2948 } 2949 else 2950 { 2951 XGI_SetRegANDOR((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */ 2952 } 2953 2954 } 2955 2956 } 2957} 2958 2959 2960void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2961{ 2962 2963 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */ 2964 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2965 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2966 2967 /* pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ; */ 2968 pVBInfo->BaseAddr = ( ULONG )HwDeviceExtension->pjIOAddress ; 2969 2970 pVBInfo->RelIO = HwDeviceExtension->pjIOAddress - 0x30; 2971 pVBInfo->ISXPDOS = 0 ; 2972 2973 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2974 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2975 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2976 2977 pVBInfo->P3cc = pVBInfo->BaseAddr + 0x1c ; /* Jong 07/31/2009 */ 2978 PDEBUG(ErrorF("XGINew_InitVBIOSData()-pVBInfo->P3cc = %d\n", pVBInfo->P3cc)); 2979 2980 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2981 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2982 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2983 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2984 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2985 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2986 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2987 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2988 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2989 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2990 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2991 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2992 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2993 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2994 2995 pVBInfo->IF_DEF_LCDA = 1 ; 2996 pVBInfo->IF_DEF_VideoCapture = 0 ; 2997 pVBInfo->IF_DEF_ScaleLCD = 0 ; 2998 pVBInfo->IF_DEF_OEMUtil = 0 ; 2999 pVBInfo->IF_DEF_PWD = 0 ; 3000 3001 if ( HwDeviceExtension->jChipType >= XG20 ) /* kuku 2004/06/25 */ 3002 { 3003 pVBInfo->IF_DEF_YPbPr = 0 ; 3004 pVBInfo->IF_DEF_HiVision = 0 ; 3005 pVBInfo->IF_DEF_CRT2Monitor = 0 ; 3006 } 3007 else if ( HwDeviceExtension->jChipType >= XG40 ) 3008 { 3009 pVBInfo->IF_DEF_YPbPr = 1 ; 3010 pVBInfo->IF_DEF_HiVision = 1 ; 3011 pVBInfo->IF_DEF_CRT2Monitor = 1 ; 3012 } 3013 else 3014 { 3015 pVBInfo->IF_DEF_YPbPr = 1 ; 3016 pVBInfo->IF_DEF_HiVision = 1 ; 3017 pVBInfo->IF_DEF_CRT2Monitor = 0 ; 3018 } 3019 3020 if ( (HwDeviceExtension->jChipType != XG20) && 3021 (HwDeviceExtension->jChipType != XG21) && 3022 (HwDeviceExtension->jChipType != XG27)) { 3023 /* alan, disable VideoCapture */ 3024 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); 3025 } 3026 3027 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */ 3028 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 3029} 3030 3031 3032/* --------------------------------------------------------------------- */ 3033/* Function : ReadVBIOSTablData */ 3034/* Input : */ 3035/* Output : */ 3036/* Description : */ 3037/* --------------------------------------------------------------------- */ 3038void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo) 3039{ 3040#ifndef LINUX_XF86 3041 ULONG ulOffset ; 3042 UCHAR temp , index , l ; 3043#endif 3044 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3045 ULONG i ; 3046 UCHAR j , k ; 3047 ULONG ii , jj ; 3048 3049 /* Jong@08212009; no valid address of VBIOS ROM */ 3050 if(pVideoMemory == NULL) 3051 { 3052 ErrorF("XGI - No valid address of VBIOS ROM!\n"); 3053 return; 3054 } 3055 else 3056 ErrorF("XGI - Read data from VBIOS ROM...\n"); 3057 3058 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */ 3059 if ( i != 0 ) 3060 UNIROM = 1 ; 3061 3062 ii = 0x90 ; 3063 for( jj = 0x00 ; jj < 0x08 ; jj++ ) 3064 { 3065 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ; 3066 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ; 3067 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ; 3068 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ; 3069 ii += 0x05 ; 3070 } 3071 3072 ii = 0xB8 ; 3073 for( jj = 0x00 ; jj < 0x08 ; jj++ ) 3074 { 3075 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ; 3076 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ; 3077 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ; 3078 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ; 3079 ii += 0x05 ; 3080 } 3081 3082 /* Volari customize data area start */ 3083 /* if ( ChipType == XG40 ) */ 3084 if ( ChipType >= XG40 ) 3085 { 3086 ii = 0xE0 ; 3087 for( jj = 0x00 ; jj < 0x03 ; jj++ ) 3088 { 3089 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */ 3090 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3091 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3092 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3093 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3094 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3095 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3096 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3097 ii += 0x08 ; 3098 } 3099 ii = 0x110 ; 3100 jj = 0x03 ; 3101 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */ 3102 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3103 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3104 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3105 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3106 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3107 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3108 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3109 3110 pVBInfo->SR07 = pVideoMemory[0x74]; 3111 pVBInfo->SR1F = pVideoMemory[0x75]; 3112 pVBInfo->SR21 = pVideoMemory[0x76]; 3113 pVBInfo->SR22 = pVideoMemory[0x77]; 3114 pVBInfo->SR23 = pVideoMemory[0x78]; 3115 pVBInfo->SR24 = pVideoMemory[0x79]; 3116 pVBInfo->SR25[0] = pVideoMemory[0x7A]; 3117 pVBInfo->SR31 = pVideoMemory[0x7B]; 3118 pVBInfo->SR32 = pVideoMemory[0x7C]; 3119 pVBInfo->SR33 = pVideoMemory[0x7D]; 3120 ii = 0xF8 ; 3121 3122 for( jj = 0 ; jj < 3 ; jj++ ) 3123 { 3124 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ; 3125 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3126 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3127 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3128 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3129 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3130 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3131 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3132 ii += 0x08 ; 3133 } 3134 3135 ii = 0x118 ; 3136 for( j = 3 ; j < 24 ; j++ ) 3137 { 3138 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ; 3139 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3140 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3141 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3142 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3143 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3144 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3145 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3146 ii += 0x08 ; 3147 } 3148 3149 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ; 3150 3151 for( j = 0 ; j < 8 ; j++ ) 3152 { 3153 for( k = 0 ; k < 4 ; k++ ) 3154 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ; 3155 } 3156 3157 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ; 3158 3159 if (ChipType == XG45) 3160 { 3161 for( j = 0 ; j < 8 ; j++ ) 3162 { 3163 pVBInfo->XG45CR6E[ j ] = pVideoMemory[i] ; 3164 } 3165 } 3166 else 3167 { 3168 for( j = 0 ; j < 8 ; j++ ) 3169 { 3170 for( k = 0 ; k < 4 ; k++ ) 3171 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ; 3172 } 3173 } 3174 3175 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ; 3176 if (ChipType == XG45) 3177 { 3178 for( j = 0 ; j < 8 ; j++ ) 3179 { 3180 pVBInfo->XG45CR6F[ j ] = pVideoMemory[i] ; 3181 } 3182 } 3183 else 3184 { 3185 for( j = 0 ; j < 8 ; j++ ) 3186 { 3187 for( k = 0 ; k < 32 ; k++ ) 3188 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ; 3189 } 3190 } 3191 3192 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ; 3193 3194 for( j = 0 ; j < 8 ; j++ ) 3195 { 3196 for( k = 0 ; k < 2 ; k++ ) 3197 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ; 3198 } 3199 3200 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ; 3201 for( j = 0 ; j < 12 ; j++ ) 3202 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ; 3203 3204 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; 3205 for( j = 0 ; j < 4 ; j++ ) 3206 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ; 3207 3208 /* Jong 10/03/2007 */ 3209 /* 3210 pVBInfo->CRCF = pVideoMemory[0x1CA]; 3211 pVBInfo->DRAMTypeDefinition = pVideoMemory[0x1CB]; 3212 pVBInfo->I2CDefinition = pVideoMemory[0x1D1]; 3213 if ( ChipType == XG20 ) 3214 pVBInfo->CR97 = pVideoMemory[0x1D2]; */ 3215 if ( ChipType == XG21 ) 3216 { 3217 if (pVideoMemory[ 0x67 ] & 0x80) 3218 { 3219 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ]; 3220 } 3221 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 ) 3222 { 3223 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ; 3224 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ; 3225 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ; 3226 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ; 3227 } 3228 } 3229 3230 if ( ChipType == XG27 ) 3231 { 3232 jj = i+j; 3233 for( i = 0 ; i <= 0xB ; i++,jj++ ) 3234 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ; 3235 for( i = 0x0 ; i <= 0x1 ; i++,jj++ ) 3236 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ; 3237 3238 *pVBInfo->pSR40 = pVideoMemory[ jj ] ; 3239 jj++; 3240 *pVBInfo->pSR41 = pVideoMemory[ jj ] ; 3241 3242 if (pVideoMemory[ 0x67 ] & 0x80) 3243 { 3244 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ]; 3245 } 3246 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 ) 3247 { 3248 jj++; 3249 *pVBInfo->pCR2E = pVideoMemory[ jj ] ; 3250 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ; 3251 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ; 3252 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ; 3253 } 3254 3255 } 3256 3257 pVBInfo->CRCF = pVideoMemory[ 0x1CA ] ; 3258 pVBInfo->DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ; 3259 pVBInfo->I2CDefinition = pVideoMemory[ 0x1D1 ] ; 3260 if ( ChipType >= XG20 ) 3261 { 3262 pVBInfo->CR97 = pVideoMemory[ 0x1D2 ] ; 3263 if ( ChipType == XG27 ) 3264 { 3265 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ; 3266 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ; 3267 } 3268 } 3269 } 3270 /* Volari customize data area end */ 3271 3272 if ( ChipType == XG21 ) 3273 { 3274 pVBInfo->IF_DEF_LVDS = 0 ; 3275 if (pVideoMemory[ 0x65 ] & 0x1) 3276 { 3277 pVBInfo->IF_DEF_LVDS = 1 ; 3278 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 ); 3279 j = pVideoMemory[ i-1 ] ; 3280 if ( j != 0xff ) 3281 { 3282 k = 0; 3283 do 3284 { 3285 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3286 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3287 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3288 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3289 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3290 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3291 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3292 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3293 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3294 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ; 3295 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ; 3296 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ; 3297 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ; 3298 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ; 3299 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ; 3300 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ; 3301 i += 25; 3302 j--; 3303 k++; 3304 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) ); 3305 } 3306 else 3307 { 3308 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3309 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3310 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3311 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3312 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3313 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3314 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3315 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3316 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3317 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ; 3318 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ; 3319 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ; 3320 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ; 3321 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ; 3322 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ; 3323 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ; 3324 } 3325 } 3326 pVBInfo->IF_DEF_CH7007 = 0 ; 3327 if ( ( pVideoMemory[ 0x65 ] & 0x02 ) ) /* For XG21 CH7007 */ 3328 { 3329 /* VideoDebugPrint((0, "ReadVBIOSTablData: pVideoMemory[ 0x65 ] =%x\n",pVideoMemory[ 0x65 ])); */ 3330 pVBInfo->IF_DEF_CH7007 = 1 ; /* [Billy] 07/05/03 */ 3331 } 3332 } 3333 3334 if ( ChipType == XG27 ) 3335 { 3336 if (pVideoMemory[ 0x65 ] & 0x1) 3337 { 3338 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 ); 3339 j = pVideoMemory[ i-1 ] ; 3340 if ( j != 0xff ) 3341 { 3342 k = 0; 3343 do 3344 { 3345 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3346 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3347 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3348 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3349 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3350 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3351 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3352 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3353 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3354 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ; 3355 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ; 3356 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ; 3357 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ; 3358 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ; 3359 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ; 3360 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ; 3361 i += 25; 3362 j--; 3363 k++; 3364 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) ); 3365 } 3366 else 3367 { 3368 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3369 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3370 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3371 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3372 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3373 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3374 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3375 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3376 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3377 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ; 3378 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ; 3379 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ; 3380 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ; 3381 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ; 3382 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ; 3383 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ; 3384 } 3385 } 3386 } 3387 3388 ErrorF("XGI - Read data from VBIOS ROM...End\n"); 3389} 3390 3391/* --------------------------------------------------------------------- */ 3392/* Function : XGINew_DDR1x_MRS_XG20 */ 3393/* Input : */ 3394/* Output : */ 3395/* Description : */ 3396/* --------------------------------------------------------------------- */ 3397void XGINew_DDR1x_MRS_XG20( USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 3398{ 3399 3400 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ; 3401 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 3402 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 3403 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 3404 DelayUS( 60 ) ; 3405 3406 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 3407 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 3408 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 3409 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 3410 DelayUS( 60 ) ; 3411 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 3412 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 3413 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ; 3414 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ; 3415 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; 3416 DelayUS( 1000 ) ; 3417 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 3418 DelayUS( 500 ) ; 3419 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 3420 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 3421 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 3422 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ; 3423 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; 3424 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 3425} 3426 3427/* --------------------------------------------------------------------- */ 3428/* Function : XGINew_SetDRAMModeRegister_XG20 */ 3429/* Input : */ 3430/* Output : */ 3431/* Description : */ 3432/* --------------------------------------------------------------------- */ 3433void XGINew_SetDRAMModeRegister_XG20(PXGI_HW_DEVICE_INFO HwDeviceExtension, 3434 PVB_DEVICE_INFO pVBInfo) 3435{ 3436#ifndef LINUX_XF86 3437 UCHAR data ; 3438#endif 3439 3440 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 3441 3442 if ( XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 3443 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 3444 else 3445 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 3446 3447 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ; 3448} 3449 3450void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension ) 3451{ 3452#ifndef LINUX_XF86 3453 UCHAR data ; 3454#endif 3455 VB_DEVICE_INFO VBINF; 3456 PVB_DEVICE_INFO pVBInfo = &VBINF; 3457 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 3458 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 3459 pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ; 3460 pVBInfo->ISXPDOS = 0 ; 3461 3462 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 3463 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 3464 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 3465 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 3466 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 3467 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 3468 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 3469 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 3470 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 3471 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 3472 3473 pVBInfo->P3cc = pVBInfo->BaseAddr + 0x1c ; /* Jong 07/31/2009 */ 3474 PDEBUG(ErrorF("XGINew_SetDRAMModeRegister_XG27()-pVBInfo->P3cc = %d\n", pVBInfo->P3cc)); 3475 3476 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 3477 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 3478 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 3479 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 3480 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 3481 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 3482 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 3483 3484 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 3485 3486 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 3487 3488 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 3489 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 3490 else 3491 /*XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;*/ 3492 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ; 3493 3494 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;*/ 3495 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 3496 3497} 3498 3499/* -------------------------------------------------------- */ 3500/* Function : XGINew_ChkSenseStatus */ 3501/* Input : */ 3502/* Output : */ 3503/* Description : */ 3504/* -------------------------------------------------------- */ 3505void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 3506{ 3507 USHORT tempbx=0 , temp , tempcx , CR3CData; 3508 3509 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 ) ; 3510 3511 if ( temp & Monitor1Sense ) 3512 tempbx |= ActiveCRT1 ; 3513 if ( temp & LCDSense ) 3514 tempbx |= ActiveLCD ; 3515 if ( temp & Monitor2Sense ) 3516 tempbx |= ActiveCRT2 ; 3517 if ( temp & TVSense ) 3518 { 3519 tempbx |= ActiveTV ; 3520 if ( temp & AVIDEOSense ) 3521 tempbx |= ( ActiveAVideo << 8 ); 3522 if ( temp & SVIDEOSense ) 3523 tempbx |= ( ActiveSVideo << 8 ); 3524 if ( temp & SCARTSense ) 3525 tempbx |= ( ActiveSCART << 8 ); 3526 if ( temp & HiTVSense ) 3527 tempbx |= ( ActiveHiTV << 8 ); 3528 if ( temp & YPbPrSense ) 3529 tempbx |= ( ActiveYPbPr << 8 ); 3530 } 3531 3532 tempcx = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ; 3533 tempcx |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ) ; 3534 3535 if ( tempbx & tempcx ) 3536 { 3537 CR3CData = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3c ) ; 3538 if ( !( CR3CData & DisplayDeviceFromCMOS ) ) 3539 { 3540 tempcx = 0x1FF0 ; 3541 if (pVBInfo->SoftSetting & ModeSoftSetting) { 3542 tempbx = 0x1FF0 ; 3543 } 3544 } 3545 } 3546 else 3547 { 3548 tempcx = 0x1FF0 ; 3549 if (pVBInfo->SoftSetting & ModeSoftSetting) { 3550 tempbx = 0x1FF0 ; 3551 } 3552 } 3553 3554 tempbx &= tempcx ; 3555 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ; 3556 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ; 3557} 3558/* -------------------------------------------------------- */ 3559/* Function : XGINew_SetModeScratch */ 3560/* Input : */ 3561/* Output : */ 3562/* Description : */ 3563/* -------------------------------------------------------- */ 3564void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) 3565{ 3566 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data; 3567 3568 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ; 3569 temp |= XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ; 3570 temp |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ; 3571 3572 if ( pVBInfo->IF_DEF_CRT2Monitor == 1) 3573 { 3574 if ( temp & ActiveCRT2 ) 3575 tempcl = SetCRT2ToRAMDAC ; 3576 } 3577 3578 if ( temp & ActiveLCD ) 3579 { 3580 tempcl |= SetCRT2ToLCD ; 3581 if ( temp & DriverMode ) 3582 { 3583 if ( temp & ActiveTV ) 3584 { 3585 tempch = SetToLCDA | EnableDualEdge ; 3586 temp ^= SetCRT2ToLCD ; 3587 3588 if ( ( temp >> 8 ) & ActiveAVideo ) 3589 tempcl |= SetCRT2ToAVIDEO ; 3590 if ( ( temp >> 8 ) & ActiveSVideo ) 3591 tempcl |= SetCRT2ToSVIDEO ; 3592 if ( ( temp >> 8 ) & ActiveSCART ) 3593 tempcl |= SetCRT2ToSCART ; 3594 3595 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3596 { 3597 if ( ( temp >> 8 ) & ActiveHiTV ) 3598 tempcl |= SetCRT2ToHiVisionTV ; 3599 } 3600 3601 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3602 { 3603 if ( ( temp >> 8 ) & ActiveYPbPr ) 3604 tempch |= SetYPbPr ; 3605 } 3606 } 3607 } 3608 } 3609 else 3610 { 3611 if ( ( temp >> 8 ) & ActiveAVideo ) 3612 tempcl |= SetCRT2ToAVIDEO ; 3613 if ( ( temp >> 8 ) & ActiveSVideo ) 3614 tempcl |= SetCRT2ToSVIDEO ; 3615 if ( ( temp >> 8 ) & ActiveSCART ) 3616 tempcl |= SetCRT2ToSCART ; 3617 3618 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3619 { 3620 if ( ( temp >> 8 ) & ActiveHiTV ) 3621 tempcl |= SetCRT2ToHiVisionTV ; 3622 } 3623 3624 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3625 { 3626 if ( ( temp >> 8 ) & ActiveYPbPr ) 3627 tempch |= SetYPbPr ; 3628 } 3629 } 3630 3631 tempcl |= SetSimuScanMode ; 3632 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3633 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3634 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) ) 3635 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3636 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x30 , tempcl ) ; 3637 3638 CR31Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) ; 3639 CR31Data &= ~( SetNotSimuMode >> 8 ) ; 3640 if ( !( temp & ActiveCRT1 ) ) 3641 CR31Data |= ( SetNotSimuMode >> 8 ) ; 3642 CR31Data &= ~( DisableCRT2Display >> 8 ) ; 3643 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3644 CR31Data |= ( DisableCRT2Display >> 8 ) ; 3645 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x31 , CR31Data ) ; 3646 3647 CR38Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ; 3648 CR38Data &= ~SetYPbPr ; 3649 CR38Data |= tempch ; 3650 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x38 , CR38Data ) ; 3651 3652} 3653 3654/* -------------------------------------------------------- */ 3655/* Function : XGINew_GetXG21Sense */ 3656/* Input : */ 3657/* Output : */ 3658/* Description : */ 3659/* -------------------------------------------------------- */ 3660void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 3661{ 3662 UCHAR Temp; 3663 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3664 3665 pVBInfo->IF_DEF_LVDS = 0 ; 3666 3667 if ( ( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */ 3668 { 3669 pVBInfo->IF_DEF_LVDS = 1 ; 3670 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3671 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */ 3672 } 3673 else 3674 { 3675 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */ 3676 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0xC0; 3677 if ( Temp == 0xC0 ) 3678 { /* DVI & DVO GPIOA/B pull high */ 3679 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ; 3680 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3681 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */ 3682 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x04 ; 3683 if ( !Temp ) 3684 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */ 3685 else 3686 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */ 3687 3688 XGI_SetRegAND( (XGIIOADDRESS)pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */ 3689 } 3690 } 3691} 3692 3693/* -------------------------------------------------------- */ 3694/* Function : XGINew_GetXG27Sense */ 3695/* Input : */ 3696/* Output : */ 3697/* Description : */ 3698/* -------------------------------------------------------- */ 3699void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 3700{ 3701 UCHAR Temp,bCR4A; 3702 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3703 3704 pVBInfo->IF_DEF_LVDS = 0 ; 3705 bCR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3706 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */ 3707 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x07; 3708 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , bCR4A ) ; 3709 3710 if ( Temp <= 0x02 ) 3711 { 3712 pVBInfo->IF_DEF_LVDS = 1 ; 3713 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */ 3714 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x30 , 0x21 ) ; 3715 } 3716 else 3717 { 3718 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */ 3719 } 3720 3721 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3722} 3723 3724UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo) 3725{ 3726 UCHAR CR38,CR4A,temp; 3727 3728 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3729 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */ 3730 CR38 = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ; 3731 temp =0; 3732 if ( ( CR38 & 0xE0 ) > 0x80 ) 3733 { 3734 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; 3735 temp &= 0x08; 3736 temp >>= 3; 3737 } 3738 3739 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ; 3740 3741 return temp; 3742} 3743 3744UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo) 3745{ 3746 UCHAR CR38,CR4A,temp; 3747 3748 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3749 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */ 3750 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; 3751 if ( temp <= 2 ) 3752 { 3753 temp &= 0x03; 3754 } 3755 else 3756 { 3757 temp = ((temp&0x04)>>1) || ((~temp)&0x01); 3758 } 3759 3760 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ; 3761 3762 return temp; 3763} 3764 3765