1 2#include <xf86RamDac.h> 3 4extern _X_EXPORT RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); 5extern _X_EXPORT void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); 6extern _X_EXPORT void IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); 7extern _X_EXPORT void IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); 8extern _X_EXPORT void IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); 9extern _X_EXPORT unsigned long IBMramdac526CalculateMNPCForClock(unsigned long RefClock, 10 unsigned long ReqClock, char IsPixClock, unsigned long MinClock, 11 unsigned long MaxClock, unsigned long *rM, unsigned long *rN, 12 unsigned long *rP, unsigned long *rC); 13extern _X_EXPORT unsigned long IBMramdac640CalculateMNPCForClock(unsigned long RefClock, 14 unsigned long ReqClock, char IsPixClock, unsigned long MinClock, 15 unsigned long MaxClock, unsigned long *rM, unsigned long *rN, 16 unsigned long *rP, unsigned long *rC); 17extern _X_EXPORT void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr); 18extern _X_EXPORT void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr); 19 20typedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr); 21extern _X_EXPORT IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void); 22 23#define IBM524_RAMDAC ((VENDOR_IBM << 16) | 0x00) 24#define IBM524A_RAMDAC ((VENDOR_IBM << 16) | 0x01) 25#define IBM525_RAMDAC ((VENDOR_IBM << 16) | 0x02) 26#define IBM526_RAMDAC ((VENDOR_IBM << 16) | 0x03) 27#define IBM526DB_RAMDAC ((VENDOR_IBM << 16) | 0x04) 28#define IBM528_RAMDAC ((VENDOR_IBM << 16) | 0x05) 29#define IBM528A_RAMDAC ((VENDOR_IBM << 16) | 0x06) 30#define IBM624_RAMDAC ((VENDOR_IBM << 16) | 0x07) 31#define IBM624DB_RAMDAC ((VENDOR_IBM << 16) | 0x08) 32#define IBM640_RAMDAC ((VENDOR_IBM << 16) | 0x09) 33 34/* 35 * IBM Ramdac registers 36 */ 37 38#define IBMRGB_REF_FREQ_1 14.31818 39#define IBMRGB_REF_FREQ_2 50.00000 40 41#define IBMRGB_rev 0x00 42#define IBMRGB_id 0x01 43#define IBMRGB_misc_clock 0x02 44#define IBMRGB_sync 0x03 45#define IBMRGB_hsync_pos 0x04 46#define IBMRGB_pwr_mgmt 0x05 47#define IBMRGB_dac_op 0x06 48#define IBMRGB_pal_ctrl 0x07 49#define IBMRGB_sysclk 0x08 /* not RGB525 */ 50#define IBMRGB_pix_fmt 0x0a 51#define IBMRGB_8bpp 0x0b 52#define IBMRGB_16bpp 0x0c 53#define IBMRGB_24bpp 0x0d 54#define IBMRGB_32bpp 0x0e 55#define IBMRGB_pll_ctrl1 0x10 56#define IBMRGB_pll_ctrl2 0x11 57#define IBMRGB_pll_ref_div_fix 0x14 58#define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */ 59#define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */ 60/* #define IBMRGB_f0 0x20 */ 61 62#define IBMRGB_sysclk_n 0x15 63#define IBMRGB_sysclk_m 0x16 64#define IBMRGB_sysclk_p 0x17 65#define IBMRGB_sysclk_c 0x18 66 67#define IBMRGB_m0 0x20 68#define IBMRGB_n0 0x21 69#define IBMRGB_p0 0x22 70#define IBMRGB_c0 0x23 71#define IBMRGB_m1 0x24 72#define IBMRGB_n1 0x25 73#define IBMRGB_p1 0x26 74#define IBMRGB_c1 0x27 75#define IBMRGB_m2 0x28 76#define IBMRGB_n2 0x29 77#define IBMRGB_p2 0x2a 78#define IBMRGB_c2 0x2b 79#define IBMRGB_m3 0x2c 80#define IBMRGB_n3 0x2d 81#define IBMRGB_p3 0x2e 82#define IBMRGB_c3 0x2f 83 84#define IBMRGB_curs 0x30 85#define IBMRGB_curs_xl 0x31 86#define IBMRGB_curs_xh 0x32 87#define IBMRGB_curs_yl 0x33 88#define IBMRGB_curs_yh 0x34 89#define IBMRGB_curs_hot_x 0x35 90#define IBMRGB_curs_hot_y 0x36 91#define IBMRGB_curs_col1_r 0x40 92#define IBMRGB_curs_col1_g 0x41 93#define IBMRGB_curs_col1_b 0x42 94#define IBMRGB_curs_col2_r 0x43 95#define IBMRGB_curs_col2_g 0x44 96#define IBMRGB_curs_col2_b 0x45 97#define IBMRGB_curs_col3_r 0x46 98#define IBMRGB_curs_col3_g 0x47 99#define IBMRGB_curs_col3_b 0x48 100#define IBMRGB_border_col_r 0x60 101#define IBMRGB_border_col_g 0x61 102#define IBMRGB_botder_col_b 0x62 103#define IBMRGB_key 0x68 104#define IBMRGB_key_mask 0x6C 105#define IBMRGB_misc1 0x70 106#define IBMRGB_misc2 0x71 107#define IBMRGB_misc3 0x72 108#define IBMRGB_misc4 0x73 /* not RGB525 */ 109#define IBMRGB_key_control 0x78 110#define IBMRGB_dac_sense 0x82 111#define IBMRGB_misr_r 0x84 112#define IBMRGB_misr_g 0x86 113#define IBMRGB_misr_b 0x88 114#define IBMRGB_pll_vco_div_in 0x8e 115#define IBMRGB_pll_ref_div_in 0x8f 116#define IBMRGB_vram_mask_0 0x90 117#define IBMRGB_vram_mask_1 0x91 118#define IBMRGB_vram_mask_2 0x92 119#define IBMRGB_vram_mask_3 0x93 120#define IBMRGB_curs_array 0x100 121 122 123 124/* Constants rgb525.h */ 125 126/* RGB525_REVISION_LEVEL */ 127#define RGB525_PRODUCT_REV_LEVEL 0xf0 128 129/* RGB525_ID */ 130#define RGB525_PRODUCT_ID 0x01 131 132/* RGB525_MISC_CTRL_1 */ 133#define MISR_CNTL_ENABLE 0x80 134#define VMSK_CNTL_ENABLE 0x40 135#define PADR_RDMT_RDADDR 0x0 136#define PADR_RDMT_PAL_STATE 0x20 137#define SENS_DSAB_DISABLE 0x10 138#define SENS_SEL_BIT3 0x0 139#define SENS_SEL_BIT7 0x08 140#define VRAM_SIZE_32 0x0 141#define VRAM_SIZE_64 0x01 142 143/* RGB525_MISC_CTRL_2 */ 144#define PCLK_SEL_LCLK 0x0 145#define PCLK_SEL_PLL 0x40 146#define PCLK_SEL_EXT 0x80 147#define INTL_MODE_ENABLE 0x20 148#define BLANK_CNTL_ENABLE 0x10 149#define COL_RES_6BIT 0x0 150#define COL_RES_8BIT 0x04 151#define PORT_SEL_VGA 0x0 152#define PORT_SEL_VRAM 0x01 153 154/* RGB525_MISC_CTRL_3 */ 155#define SWAP_RB 0x80 156#define SWAP_WORD_LOHI 0x0 157#define SWAP_WORD_HILO 0x10 158#define SWAP_NIB_HILO 0x0 159#define SWAP_NIB_LOHI 0x02 160 161/* RGB525_MISC_CLK_CTRL */ 162#define DDOT_CLK_ENABLE 0x0 163#define DDOT_CLK_DISABLE 0x80 164#define SCLK_ENABLE 0x0 165#define SCLK_DISABLE 0x40 166#define B24P_DDOT_PLL 0x0 167#define B24P_DDOT_SCLK 0x20 168#define DDOT_DIV_PLL_1 0x0 169#define DDOT_DIV_PLL_2 0x02 170#define DDOT_DIV_PLL_4 0x04 171#define DDOT_DIV_PLL_8 0x06 172#define DDOT_DIV_PLL_16 0x08 173#define PLL_DISABLE 0x0 174#define PLL_ENABLE 0x01 175 176/* RGB525_SYNC_CTRL */ 177#define DLY_CNTL_ADD 0x0 178#define DLY_SYNC_NOADD 0x80 179#define CSYN_INVT_DISABLE 0x0 180#define CSYN_INVT_ENABLE 0x40 181#define VSYN_INVT_DISABLE 0x0 182#define VSYN_INVT_ENABLE 0x20 183#define HSYN_INVT_DISABLE 0x0 184#define HSYN_INVT_ENABLE 0x10 185#define VSYN_CNTL_NORMAL 0x0 186#define VSYN_CNTL_HIGH 0x04 187#define VSYN_CNTL_LOW 0x08 188#define VSYN_CNTL_DISABLE 0x0C 189#define HSYN_CNTL_NORMAL 0x0 190#define HSYN_CNTL_HIGH 0x01 191#define HSYN_CNTL_LOW 0x02 192#define HSYN_CNTL_DISABLE 0x03 193 194/* RGB525_HSYNC_CTRL */ 195#define HSYN_POS(n) (n) 196 197/* RGB525_POWER_MANAGEMENT */ 198#define SCLK_PWR_NORMAL 0x0 199#define SCLK_PWR_DISABLE 0x10 200#define DDOT_PWR_NORMAL 0x0 201#define DDOT_PWR_DISABLE 0x08 202#define SYNC_PWR_NORMAL 0x0 203#define SYNC_PWR_DISABLE 0x04 204#define ICLK_PWR_NORMAL 0x0 205#define ICLK_PWR_DISABLE 0x02 206#define DAC_PWR_NORMAL 0x0 207#define DAC_PWR_DISABLE 0x01 208 209/* RGB525_DAC_OPERATION */ 210#define SOG_DISABLE 0x0 211#define SOG_ENABLE 0x08 212#define BRB_NORMAL 0x0 213#define BRB_ALWAYS 0x04 214#define DSR_DAC_SLOW 0x02 215#define DSR_DAC_FAST 0x0 216#define DPE_DISABLE 0x0 217#define DPE_ENABLE 0x01 218 219/* RGB525_PALETTE_CTRL */ 220#define SIXBIT_LINEAR_ENABLE 0x0 221#define SIXBIT_LINEAR_DISABLE 0x80 222#define PALETTE_PARITION(n) (n) 223 224/* RGB525_PIXEL_FORMAT */ 225#define PIXEL_FORMAT_4BPP 0x02 226#define PIXEL_FORMAT_8BPP 0x03 227#define PIXEL_FORMAT_16BPP 0x04 228#define PIXEL_FORMAT_24BPP 0x05 229#define PIXEL_FORMAT_32BPP 0x06 230 231/* RGB525_8BPP_CTRL */ 232#define B8_DCOL_INDIRECT 0x0 233#define B8_DCOL_DIRECT 0x01 234 235/* RGB525_16BPP_CTRL */ 236#define B16_DCOL_INDIRECT 0x0 237#define B16_DCOL_DYNAMIC 0x40 238#define B16_DCOL_DIRECT 0xC0 239#define B16_POL_FORCE_BYPASS 0x0 240#define B16_POL_FORCE_LOOKUP 0x20 241#define B16_ZIB 0x0 242#define B16_LINEAR 0x04 243#define B16_555 0x0 244#define B16_565 0x02 245#define B16_SPARSE 0x0 246#define B16_CONTIGUOUS 0x01 247 248/* RGB525_24BPP_CTRL */ 249#define B24_DCOL_INDIRECT 0x0 250#define B24_DCOL_DIRECT 0x01 251 252/* RGB525_32BPP_CTRL */ 253#define B32_POL_FORCE_BYPASS 0x0 254#define B32_POL_FORCE_LOOKUP 0x04 255#define B32_DCOL_INDIRECT 0x0 256#define B32_DCOL_DYNAMIC 0x01 257#define B32_DCOL_DIRECT 0x03 258 259/* RGB525_PLL_CTRL_1 */ 260#define REF_SRC_REFCLK 0x0 261#define REF_SRC_EXTCLK 0x10 262#define PLL_EXT_FS_3_0 0x0 263#define PLL_EXT_FS_2_0 0x01 264#define PLL_CNTL2_3_0 0x02 265#define PLL_CNTL2_2_0 0x03 266 267/* RGB525_PLL_CTRL_2 */ 268#define PLL_INT_FS_3_0(n) (n) 269#define PLL_INT_FS_2_0(n) (n) 270 271/* RGB525_PLL_REF_DIV_COUNT */ 272#define REF_DIV_COUNT(n) (n) 273 274/* RGB525_F0 - RGB525_F15 */ 275#define VCO_DIV_COUNT(n) (n) 276 277/* RGB525_PLL_REFCLK values */ 278#define RGB525_PLL_REFCLK_MHz(n) ((n)/2) 279 280/* RGB525_CURSOR_CONTROL */ 281#define SMLC_PART_0 0x0 282#define SMLC_PART_1 0x40 283#define SMLC_PART_2 0x80 284#define SMLC_PART_3 0xC0 285#define PIX_ORDER_RL 0x0 286#define PIX_ORDER_LR 0x20 287#define LOC_READ_LAST 0x0 288#define LOC_READ_ACTUAL 0x10 289#define UPDT_CNTL_DELAYED 0x0 290#define UPDT_CNTL_IMMEDIATE 0x08 291#define CURSOR_SIZE_32 0x0 292#define CURSOR_SIZE_64 0x40 293#define CURSOR_MODE_OFF 0x0 294#define CURSOR_MODE_3_COLOR 0x01 295#define CURSOR_MODE_2_COLOR_HL 0x02 296#define CURSOR_MODE_2_COLOR 0x03 297 298/* RGB525_REVISION_LEVEL */ 299#define REVISION_LEVEL 0xF0 /* predefined */ 300 301/* RGB525_ID */ 302#define ID_CODE 0x01 /* predefined */ 303 304/* MISR status */ 305#define RGB525_MISR_DONE 0x01 306 307/* the IBMRGB640 is rather different from the rest of the RAMDACs, 308 so we define a completely new set of register names for it */ 309#define RGB640_SER_07_00 0x02 310#define RGB640_SER_15_08 0x03 311#define RGB640_SER_23_16 0x04 312#define RGB640_SER_31_24 0x05 313#define RGB640_SER_WID_03_00 0x06 314#define RGB640_SER_WID_07_04 0x07 315#define RGB640_SER_MODE 0x08 316#define IBM640_SER_2_1 0x00 317#define IBM640_SER_4_1 0x01 318#define IBM640_SER_8_1 0x02 319#define IBM640_SER_16_1 0x03 320#define IBM640_SER_16_3 0x05 321#define IBM640_SER_5_1 0x06 322#define RGB640_PIXEL_INTERLEAVE 0x09 323#define RGB640_MISC_CONF 0x0a 324#define IBM640_PCLK 0x00 325#define IBM640_PCLK_2 0x40 326#define IBM640_PCLK_4 0x80 327#define IBM640_PCLK_8 0xc0 328#define IBM640_PSIZE10 0x10 329#define IBM640_LCI 0x08 330#define IBM640_WIDCTL_MASK 0x07 331#define RGB640_VGA_CONTROL 0x0b 332#define IBM640_RDBK 0x04 333#define IBM640_PSIZE8 0x02 334#define IBM640_VRAM 0x01 335#define RGB640_DAC_CONTROL 0x0d 336#define IBM640_MONO 0x08 337#define IBM640_DACENBL 0x04 338#define IBM640_SHUNT 0x02 339#define IBM640_SLOWSLEW 0x01 340#define RGB640_OUTPUT_CONTROL 0x0e 341#define IBM640_RDAI 0x04 342#define IBM640_WDAI 0x02 343#define IBM640_WATCTL 0x01 344#define RGB640_SYNC_CONTROL 0x0f 345#define IBM640_PWR 0x20 346#define IBM640_VSP 0x10 347#define IBM640_HSP 0x08 348#define IBM640_CSE 0x04 349#define IBM640_CSG 0x02 350#define IBM640_BPE 0x01 351#define RGB640_PLL_N 0x10 352#define RGB640_PLL_M 0x11 353#define RGB640_PLL_P 0x12 354#define RGB640_PLL_CTL 0x13 355#define IBM640_PLL_EN 0x04 356#define IBM640_PLL_HIGH 0x10 357#define IBM640_PLL_LOW 0x01 358#define RGB640_AUX_PLL_CTL 0x17 359#define IBM640_AUXPLL 0x04 360#define IBM640_AUX_HI 0x02 361#define IBM640_AUX_LO 0x01 362#define RGB640_CHROMA_KEY0 0x20 363#define RGB640_CHROMA_MASK0 0x21 364#define RGB640_CURS_X_LOW 0x40 365#define RGB640_CURS_X_HIGH 0x41 366#define RGB640_CURS_Y_LOW 0x42 367#define RGB640_CURS_Y_HIGH 0x43 368#define RGB640_CURS_OFFSETX 0x44 369#define RGB640_CURS_OFFSETY 0x45 370#define RGB640_CURSOR_CONTROL 0x4B 371#define IBM640_CURS_OFF 0x00 372#define IBM640_CURS_MODE0 0x01 373#define IBM640_CURS_MODE1 0x02 374#define IBM640_CURS_MODE2 0x03 375#define IBM640_CURS_ADV 0x04 376#define RGB640_CROSSHAIR_CONTROL 0x57 377#define RGB640_VRAM_MASK0 0xf0 378#define RGB640_VRAM_MASK1 0xf1 379#define RGB640_VRAM_MASK2 0xf2 380#define RGB640_DIAGS 0xfa 381#define RGB640_CURS_WRITE 0x1000 382#define RGB640_CURS_COL0 0x4800 383#define RGB640_CURS_COL1 0x4801 384#define RGB640_CURS_COL2 0x4802 385#define RGB640_CURS_COL3 0x4803 386