Cross Reference: /src/sys/arch/mips/cavium/dev/octeon

History log of /src/sys/arch/mips/cavium/dev/octeon_ciureg.h
Revision	Date	Author	Comments
1.11	20-Jul-2020	jmcneill	Fix coreX/IP4 summary register offsets
1.10	17-Jul-2020	jmcneill	Remove 2 CPU limit in OCTEON interrupt controller driver.
1.9	22-Jun-2020	simonb	Remove more snprintb _BITS bits.
1.8	22-Jun-2020	simonb	Remove unused snprintb format strings.
1.7	19-Jun-2020	simonb	Simplify interrupt definition: remove mostly unused masks and just configure everything using interrupt numbers.
1.6	02-Jun-2020	simonb	Add a missing entry, clean up a few other incorrect entries.
1.5	20-Aug-2016	skrll	branches: 1.5.14; Fix a couple of (unsed) definitions
1.4	06-Jun-2015	matt	Add CIU_BASE
1.3	06-Jun-2015	matt	branches: 1.3.2; Fix CUI_MBOX_{SET,CLR}1 values
1.2	01-Jun-2015	matt	Rework cavium support in preparation for MULTIPROCESSOR support
1.1	29-Apr-2015	hikaru	Initial import of Cavium Octeon and Octeon Plus SoC and specifically Ubiquiti Networks EdgeRouter LITE support. Currently the ethernet and uart are worked. This support was contributed by Internet Initiative Japan Inc.
1.3.2.4	05-Oct-2016	skrll	Sync with HEAD
1.3.2.3	22-Sep-2015	skrll	Sync with HEAD
1.3.2.2	06-Jun-2015	skrll	Sync with HEAD
1.3.2.1	06-Jun-2015	skrll	file octeon_ciureg.h was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000
1.5.14.2	03-Dec-2017	jdolecek	update from HEAD
1.5.14.1	20-Aug-2016	jdolecek	file octeon_ciureg.h was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000

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