octeon_ciureg.h revision 1.1
1 /* $NetBSD: octeon_ciureg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * CIU Registers 31 */ 32 33 #ifndef _OCTEON_CIUREG_H_ 34 #define _OCTEON_CIUREG_H_ 35 36 /* ---- register addresses */ 37 38 #define CIU_INT0_SUM0 UINT64_C(0x0001070000000000) 39 #define CIU_INT1_SUM0 UINT64_C(0x0001070000000008) 40 #define CIU_INT2_SUM0 UINT64_C(0x0001070000000010) 41 #define CIU_INT3_SUM0 UINT64_C(0x0001070000000018) 42 #define CIU_INT32_SUM0 UINT64_C(0x0001070000000100) 43 #define CIU_INT_SUM1 UINT64_C(0x0001070000000008) 44 #define CIU_INT0_EN0 UINT64_C(0x0001070000000200) 45 #define CIU_INT1_EN0 UINT64_C(0x0001070000000210) 46 #define CIU_INT2_EN0 UINT64_C(0x0001070000000220) 47 #define CIU_INT3_EN0 UINT64_C(0x0001070000000230) 48 #define CIU_INT32_EN0 UINT64_C(0x0001070000000400) 49 #define CIU_INT0_EN1 UINT64_C(0x0001070000000208) 50 #define CIU_INT1_EN1 UINT64_C(0x0001070000000218) 51 #define CIU_INT2_EN1 UINT64_C(0x0001070000000228) 52 #define CIU_INT3_EN1 UINT64_C(0x0001070000000238) 53 #define CIU_INT32_EN1 UINT64_C(0x0001070000000408) 54 #define CIU_TIM0 UINT64_C(0x0001070000000480) 55 #define CIU_TIM1 UINT64_C(0x0001070000000488) 56 #define CIU_TIM2 UINT64_C(0x0001070000000490) 57 #define CIU_TIM3 UINT64_C(0x0001070000000498) 58 #define CIU_WDOG0 UINT64_C(0x0001070000000500) 59 #define CIU_WDOG1 UINT64_C(0x0001070000000508) 60 #define CIU_PP_POKE0 UINT64_C(0x0001070000000580) 61 #define CIU_PP_POKE1 UINT64_C(0x0001070000000588) 62 #define CIU_MBOX_SET0 UINT64_C(0x0001070000000600) 63 #define CIU_MBOX_SET1 UINT64_C(0x0001070000000600) 64 #define CIU_MBOX_CLR0 UINT64_C(0x0001070000000680) 65 #define CIU_MBOX_CLR1 UINT64_C(0x0001070000000680) 66 #define CIU_PP_RST UINT64_C(0x0001070000000700) 67 #define CIU_PP_DBG UINT64_C(0x0001070000000708) 68 #define CIU_GSTOP UINT64_C(0x0001070000000710) 69 #define CIU_NMI UINT64_C(0x0001070000000718) 70 #define CIU_DINT UINT64_C(0x0001070000000720) 71 #define CIU_FUSE UINT64_C(0x0001070000000728) 72 #define CIU_BIST UINT64_C(0x0001070000000730) 73 #define CIU_SOFT_BIST UINT64_C(0x0001070000000738) 74 #define CIU_SOFT_RST UINT64_C(0x0001070000000740) 75 #define CIU_SOFT_PRST UINT64_C(0x0001070000000748) 76 #define CIU_PCI_INTA UINT64_C(0x0001070000000750) 77 78 #define CIU_INT0_SUM0_OFFSET 0x0000 79 #define CIU_INT1_SUM0_OFFSET 0x0008 80 #define CIU_INT2_SUM0_OFFSET 0x0010 81 #define CIU_INT3_SUM0_OFFSET 0x0018 82 #define CIU_INT32_SUM0_OFFSET 0x0100 83 #define CIU_INT_SUM1_OFFSET 0x0008 84 #define CIU_INT0_EN0_OFFSET 0x0200 85 #define CIU_INT1_EN0_OFFSET 0x0210 86 #define CIU_INT2_EN0_OFFSET 0x0220 87 #define CIU_INT3_EN0_OFFSET 0x0230 88 #define CIU_INT32_EN0_OFFSET 0x0400 89 #define CIU_INT0_EN1_OFFSET 0x0208 90 #define CIU_INT1_EN1_OFFSET 0x0218 91 #define CIU_INT2_EN1_OFFSET 0x0228 92 #define CIU_INT3_EN1_OFFSET 0x0238 93 #define CIU_INT32_EN1_OFFSET 0x0408 94 #define CIU_TIM0_OFFSET 0x0480 95 #define CIU_TIM1_OFFSET 0x0488 96 #define CIU_TIM2_OFFSET 0x0490 97 #define CIU_TIM3_OFFSET 0x0498 98 #define CIU_WDOG0_OFFSET 0x0500 99 #define CIU_WDOG1_OFFSET 0x0508 100 #define CIU_PP_POKE0_OFFSET 0x0580 101 #define CIU_PP_POKE1_OFFSET 0x0588 102 #define CIU_MBOX_SET0_OFFSET 0x0600 103 #define CIU_MBOX_SET1_OFFSET 0x0608 104 #define CIU_MBOX_CLR0_OFFSET 0x0680 105 #define CIU_MBOX_CLR1_OFFSET 0x0688 106 #define CIU_PP_RST_OFFSET 0x0700 107 #define CIU_PP_DBG_OFFSET 0x0708 108 #define CIU_GSTOP_OFFSET 0x0710 109 #define CIU_NMI_OFFSET 0x0718 110 #define CIU_DINT_OFFSET 0x0720 111 #define CIU_FUSE_OFFSET 0x0728 112 #define CIU_BIST_OFFSET 0x0730 113 #define CIU_SOFT_BIST_OFFSET 0x0738 114 #define CIU_SOFT_RST_OFFSET 0x0740 115 #define CIU_SOFT_PRST_OFFSET 0x0748 116 #define CIU_PCI_INTA_OFFSET 0x0750 117 118 /* ---- register bits */ 119 120 /* ``interrupt bits'' shift values */ 121 122 #define _CIU_INT_XXX_63_SHIFT 0x3f 123 #define _CIU_INT_XXX_62_SHIFT 0x3e 124 #define _CIU_INT_XXX_61_SHIFT 0x3d 125 #define _CIU_INT_XXX_60_SHIFT 0x3c 126 #define _CIU_INT_XXX_59_SHIFT 0x3b 127 #define _CIU_INT_MPI_SHIFT 0x3a 128 #define _CIU_INT_PCM_SHIFT 0x39 129 #define _CIU_INT_USB_SHIFT 0x38 130 #define _CIU_INT_TIMER_3_SHIFT 0x37 131 #define _CIU_INT_TIMER_2_SHIFT 0x36 132 #define _CIU_INT_TIMER_1_SHIFT 0x35 133 #define _CIU_INT_TIMER_0_SHIFT 0x34 134 #define _CIU_INT_XXX_51_SHIFT 0x33 135 #define _CIU_INT_IPD_DRP_SHIFT 0x32 136 #define _CIU_INT_GMX_DRP_SHIFT 0x30 137 #define _CIU_INT_TRACE_SHIFT 0x2f 138 #define _CIU_INT_RML_SHIFT 0x2e 139 #define _CIU_INT_TWSI_SHIFT 0x2d 140 #define _CIU_INT_WDOG_SUM_SHIFT 0x2c 141 #define _CIU_INT_PCI_MSI_63_48_SHIFT 0x2b 142 #define _CIU_INT_PCI_MSI_47_32_SHIFT 0x2a 143 #define _CIU_INT_PCI_MSI_31_16_SHIFT 0x29 144 #define _CIU_INT_PCI_MSI_15_0_SHIFT 0x28 145 #define _CIU_INT_PCI_INT_D_SHIFT 0x27 146 #define _CIU_INT_PCI_INT_C_SHIFT 0x26 147 #define _CIU_INT_PCI_INT_B_SHIFT 0x25 148 #define _CIU_INT_PCI_INT_A_SHIFT 0x24 149 #define _CIU_INT_UART_1_SHIFT 0x23 150 #define _CIU_INT_UART_0_SHIFT 0x22 151 #define _CIU_INT_MBOX_31_16_SHIFT 0x21 152 #define _CIU_INT_MBOX_15_0_SHIFT 0x20 153 #define _CIU_INT_GPIO_15_SHIFT 0x1f 154 #define _CIU_INT_GPIO_14_SHIFT 0x1e 155 #define _CIU_INT_GPIO_13_SHIFT 0x1d 156 #define _CIU_INT_GPIO_12_SHIFT 0x1c 157 #define _CIU_INT_GPIO_11_SHIFT 0x1b 158 #define _CIU_INT_GPIO_10_SHIFT 0x1a 159 #define _CIU_INT_GPIO_9_SHIFT 0x19 160 #define _CIU_INT_GPIO_8_SHIFT 0x18 161 #define _CIU_INT_GPIO_7_SHIFT 0x17 162 #define _CIU_INT_GPIO_6_SHIFT 0x16 163 #define _CIU_INT_GPIO_5_SHIFT 0x15 164 #define _CIU_INT_GPIO_4_SHIFT 0x14 165 #define _CIU_INT_GPIO_3_SHIFT 0x13 166 #define _CIU_INT_GPIO_2_SHIFT 0x12 167 #define _CIU_INT_GPIO_1_SHIFT 0x11 168 #define _CIU_INT_GPIO_0_SHIFT 0x10 169 #define _CIU_INT_WORKQ_15_SHIFT 0x0f 170 #define _CIU_INT_WORKQ_14_SHIFT 0x0e 171 #define _CIU_INT_WORKQ_13_SHIFT 0x0d 172 #define _CIU_INT_WORKQ_12_SHIFT 0x0c 173 #define _CIU_INT_WORKQ_11_SHIFT 0x0b 174 #define _CIU_INT_WORKQ_10_SHIFT 0x0a 175 #define _CIU_INT_WORKQ_9_SHIFT 0x09 176 #define _CIU_INT_WORKQ_8_SHIFT 0x08 177 #define _CIU_INT_WORKQ_7_SHIFT 0x07 178 #define _CIU_INT_WORKQ_6_SHIFT 0x06 179 #define _CIU_INT_WORKQ_5_SHIFT 0x05 180 #define _CIU_INT_WORKQ_4_SHIFT 0x04 181 #define _CIU_INT_WORKQ_3_SHIFT 0x03 182 #define _CIU_INT_WORKQ_2_SHIFT 0x02 183 #define _CIU_INT_WORKQ_1_SHIFT 0x01 184 185 #define CIU_INTX_SUM0_XXX_63_59 UINT64_C(0xf800000000000000) 186 #define CIU_INTX_SUM0_MPI UINT64_C(0x0400000000000000) 187 #define CIU_INTX_SUM0_PCM UINT64_C(0x0200000000000000) 188 #define CIU_INTX_SUM0_USB UINT64_C(0x0100000000000000) 189 #define CIU_INTX_SUM0_TIMER UINT64_C(0x00f0000000000000) 190 #define CIU_INTX_SUM0_TIMER_3 UINT64_C(0x0080000000000000) 191 #define CIU_INTX_SUM0_TIMER_2 UINT64_C(0x0040000000000000) 192 #define CIU_INTX_SUM0_TIMER_1 UINT64_C(0x0020000000000000) 193 #define CIU_INTX_SUM0_TIMER_0 UINT64_C(0x0010000000000000) 194 #define CIU_INTX_SUM0_XXX_51 UINT64_C(0x0008000000000000) 195 #define CIU_INTX_SUM0_IPD_DRP UINT64_C(0x0004000000000000) 196 #define CIU_INTX_SUM0_XXX_49 UINT64_C(0x0002000000000000) 197 #define CIU_INTX_SUM0_GMX_DRP UINT64_C(0x0001000000000000) 198 #define CIU_INTX_SUM0_TRACE UINT64_C(0x0000800000000000) 199 #define CIU_INTX_SUM0_RML UINT64_C(0x0000400000000000) 200 #define CIU_INTX_SUM0_TWSI UINT64_C(0x0000200000000000) 201 #define CIU_INTX_SUM0_WDOG_SUM UINT64_C(0x0000100000000000) 202 #define CIU_INTX_SUM0_PCI_MSI UINT64_C(0x00000f0000000000) 203 #define CIU_INTX_SUM0_PCI_MSI_63_48 UINT64_C(0x0000080000000000) 204 #define CIU_INTX_SUM0_PCI_MSI_47_32 UINT64_C(0x0000040000000000) 205 #define CIU_INTX_SUM0_PCI_MSI_31_16 UINT64_C(0x0000020000000000) 206 #define CIU_INTX_SUM0_PCI_MSI_15_0 UINT64_C(0x0000010000000000) 207 #define CIU_INTX_SUM0_PCI_INT UINT64_C(0x000000f000000000) 208 #define CIU_INTX_SUM0_PCI_INT_D UINT64_C(0x0000008000000000) 209 #define CIU_INTX_SUM0_PCI_INT_C UINT64_C(0x0000004000000000) 210 #define CIU_INTX_SUM0_PCI_INT_B UINT64_C(0x0000002000000000) 211 #define CIU_INTX_SUM0_PCI_INT_A UINT64_C(0x0000001000000000) 212 #define CIU_INTX_SUM0_UART UINT64_C(0x0000000c00000000) 213 #define CIU_INTX_SUM0_UART_1 UINT64_C(0x0000000800000000) 214 #define CIU_INTX_SUM0_UART_0 UINT64_C(0x0000000400000000) 215 #define CIU_INTX_SUM0_MBOX UINT64_C(0x0000000300000000) 216 #define CIU_INTX_SUM0_MBOX_31_16 UINT64_C(0x0000000200000000) 217 #define CIU_INTX_SUM0_MBOX_15_0 UINT64_C(0x0000000100000000) 218 #define CIU_INTX_SUM0_GPIO UINT64_C(0x00000000ffff0000) 219 #define CIU_INTX_SUM0_GPIO_15 UINT64_C(0x0000000080000000) 220 #define CIU_INTX_SUM0_GPIO_14 UINT64_C(0x0000000040000000) 221 #define CIU_INTX_SUM0_GPIO_13 UINT64_C(0x0000000020000000) 222 #define CIU_INTX_SUM0_GPIO_12 UINT64_C(0x0000000010000000) 223 #define CIU_INTX_SUM0_GPIO_11 UINT64_C(0x0000000008000000) 224 #define CIU_INTX_SUM0_GPIO_10 UINT64_C(0x0000000004000000) 225 #define CIU_INTX_SUM0_GPIO_9 UINT64_C(0x0000000002000000) 226 #define CIU_INTX_SUM0_GPIO_8 UINT64_C(0x0000000001000000) 227 #define CIU_INTX_SUM0_GPIO_7 UINT64_C(0x0000000000800000) 228 #define CIU_INTX_SUM0_GPIO_6 UINT64_C(0x0000000000400000) 229 #define CIU_INTX_SUM0_GPIO_5 UINT64_C(0x0000000000200000) 230 #define CIU_INTX_SUM0_GPIO_4 UINT64_C(0x0000000000100000) 231 #define CIU_INTX_SUM0_GPIO_3 UINT64_C(0x0000000000080000) 232 #define CIU_INTX_SUM0_GPIO_2 UINT64_C(0x0000000000040000) 233 #define CIU_INTX_SUM0_GPIO_1 UINT64_C(0x0000000000020000) 234 #define CIU_INTX_SUM0_GPIO_0 UINT64_C(0x0000000000010000) 235 #define CIU_INTX_SUM0_WORKQ UINT64_C(0x000000000000ffff) 236 #define CIU_INTX_SUM0_WORKQ_15 UINT64_C(0x0000000000008000) 237 #define CIU_INTX_SUM0_WORKQ_14 UINT64_C(0x0000000000004000) 238 #define CIU_INTX_SUM0_WORKQ_13 UINT64_C(0x0000000000002000) 239 #define CIU_INTX_SUM0_WORKQ_12 UINT64_C(0x0000000000001000) 240 #define CIU_INTX_SUM0_WORKQ_11 UINT64_C(0x0000000000000800) 241 #define CIU_INTX_SUM0_WORKQ_10 UINT64_C(0x0000000000000400) 242 #define CIU_INTX_SUM0_WORKQ_9 UINT64_C(0x0000000000000200) 243 #define CIU_INTX_SUM0_WORKQ_8 UINT64_C(0x0000000000000100) 244 #define CIU_INTX_SUM0_WORKQ_7 UINT64_C(0x0000000000000080) 245 #define CIU_INTX_SUM0_WORKQ_6 UINT64_C(0x0000000000000040) 246 #define CIU_INTX_SUM0_WORKQ_5 UINT64_C(0x0000000000000020) 247 #define CIU_INTX_SUM0_WORKQ_4 UINT64_C(0x0000000000000010) 248 #define CIU_INTX_SUM0_WORKQ_3 UINT64_C(0x0000000000000008) 249 #define CIU_INTX_SUM0_WORKQ_2 UINT64_C(0x0000000000000004) 250 #define CIU_INTX_SUM0_WORKQ_1 UINT64_C(0x0000000000000002) 251 #define CIU_INTX_SUM0_WORKQ_0 UINT64_C(0x0000000000000001) 252 253 #define CIU_INT_SUM1_XXX_63_1 UINT64_C(0xfffffffffffffffe) 254 #define CIU_INT_SUM1_WDOG UINT64_C(0x0000000000000001) 255 256 #define CIU_INTX_EN0_XXX_63_59 UINT64_C(0xf800000000000000) 257 #define CIU_INTX_EN0_MPI UINT64_C(0x0400000000000000) 258 #define CIU_INTX_EN0_PCM UINT64_C(0x0200000000000000) 259 #define CIU_INTX_EN0_USB UINT64_C(0x0100000000000000) 260 #define CIU_INTX_EN0_TIMER UINT64_C(0x00f0000000000000) 261 #define CIU_INTX_EN0_TIMER_3 UINT64_C(0x0080000000000000) 262 #define CIU_INTX_EN0_TIMER_2 UINT64_C(0x0040000000000000) 263 #define CIU_INTX_EN0_TIMER_1 UINT64_C(0x0020000000000000) 264 #define CIU_INTX_EN0_TIMER_0 UINT64_C(0x0010000000000000) 265 #define CIU_INTX_EN0_XXX_51 UINT64_C(0x0008000000000000) 266 #define CIU_INTX_EN0_IPD_DRP UINT64_C(0x0004000000000000) 267 #define CIU_INTX_EN0_XXX_49 UINT64_C(0x0002000000000000) 268 #define CIU_INTX_EN0_GMX_DRP UINT64_C(0x0001000000000000) 269 #define CIU_INTX_EN0_TRACE UINT64_C(0x0000800000000000) 270 #define CIU_INTX_EN0_RML UINT64_C(0x0000400000000000) 271 #define CIU_INTX_EN0_TWSI UINT64_C(0x0000200000000000) 272 #define CIU_INTX_EN0_WDOG_SUM UINT64_C(0x0000100000000000) 273 #define CIU_INTX_EN0_PCI_MSI UINT64_C(0x00000f0000000000) 274 #define CIU_INTX_EN0_PCI_MSI_63_48 UINT64_C(0x0000080000000000) 275 #define CIU_INTX_EN0_PCI_MSI_47_32 UINT64_C(0x0000040000000000) 276 #define CIU_INTX_EN0_PCI_MSI_31_16 UINT64_C(0x0000020000000000) 277 #define CIU_INTX_EN0_PCI_MSI_15_0 UINT64_C(0x0000010000000000) 278 #define CIU_INTX_EN0_PCI_INT UINT64_C(0x000000f000000000) 279 #define CIU_INTX_EN0_PCI_INT_D UINT64_C(0x0000008000000000) 280 #define CIU_INTX_EN0_PCI_INT_C UINT64_C(0x0000004000000000) 281 #define CIU_INTX_EN0_PCI_INT_B UINT64_C(0x0000002000000000) 282 #define CIU_INTX_EN0_PCI_INT_A UINT64_C(0x0000001000000000) 283 #define CIU_INTX_EN0_UART UINT64_C(0x0000000c00000000) 284 #define CIU_INTX_EN0_UART_1 UINT64_C(0x0000000800000000) 285 #define CIU_INTX_EN0_UART_0 UINT64_C(0x0000000400000000) 286 #define CIU_INTX_EN0_MBOX UINT64_C(0x0000000300000000) 287 #define CIU_INTX_EN0_MBOX_31_16 UINT64_C(0x0000000200000000) 288 #define CIU_INTX_EN0_MBOX_15_0 UINT64_C(0x0000000100000000) 289 #define CIU_INTX_EN0_GPIO UINT64_C(0x00000000ffff0000) 290 #define CIU_INTX_EN0_GPIO_15 UINT64_C(0x0000000080000000) 291 #define CIU_INTX_EN0_GPIO_14 UINT64_C(0x0000000040000000) 292 #define CIU_INTX_EN0_GPIO_13 UINT64_C(0x0000000020000000) 293 #define CIU_INTX_EN0_GPIO_12 UINT64_C(0x0000000010000000) 294 #define CIU_INTX_EN0_GPIO_11 UINT64_C(0x0000000008000000) 295 #define CIU_INTX_EN0_GPIO_10 UINT64_C(0x0000000004000000) 296 #define CIU_INTX_EN0_GPIO_9 UINT64_C(0x0000000002000000) 297 #define CIU_INTX_EN0_GPIO_8 UINT64_C(0x0000000001000000) 298 #define CIU_INTX_EN0_GPIO_7 UINT64_C(0x0000000000800000) 299 #define CIU_INTX_EN0_GPIO_6 UINT64_C(0x0000000000400000) 300 #define CIU_INTX_EN0_GPIO_5 UINT64_C(0x0000000000200000) 301 #define CIU_INTX_EN0_GPIO_4 UINT64_C(0x0000000000100000) 302 #define CIU_INTX_EN0_GPIO_3 UINT64_C(0x0000000000080000) 303 #define CIU_INTX_EN0_GPIO_2 UINT64_C(0x0000000000040000) 304 #define CIU_INTX_EN0_GPIO_1 UINT64_C(0x0000000000020000) 305 #define CIU_INTX_EN0_GPIO_0 UINT64_C(0x0000000000010000) 306 #define CIU_INTX_EN0_WORKQ UINT64_C(0x000000000000ffff) 307 #define CIU_INTX_EN0_WORKQ_15 UINT64_C(0x0000000000008000) 308 #define CIU_INTX_EN0_WORKQ_14 UINT64_C(0x0000000000004000) 309 #define CIU_INTX_EN0_WORKQ_13 UINT64_C(0x0000000000002000) 310 #define CIU_INTX_EN0_WORKQ_12 UINT64_C(0x0000000000001000) 311 #define CIU_INTX_EN0_WORKQ_11 UINT64_C(0x0000000000000800) 312 #define CIU_INTX_EN0_WORKQ_10 UINT64_C(0x0000000000000400) 313 #define CIU_INTX_EN0_WORKQ_9 UINT64_C(0x0000000000000200) 314 #define CIU_INTX_EN0_WORKQ_8 UINT64_C(0x0000000000000100) 315 #define CIU_INTX_EN0_WORKQ_7 UINT64_C(0x0000000000000080) 316 #define CIU_INTX_EN0_WORKQ_6 UINT64_C(0x0000000000000040) 317 #define CIU_INTX_EN0_WORKQ_5 UINT64_C(0x0000000000000020) 318 #define CIU_INTX_EN0_WORKQ_4 UINT64_C(0x0000000000000010) 319 #define CIU_INTX_EN0_WORKQ_3 UINT64_C(0x0000000000000008) 320 #define CIU_INTX_EN0_WORKQ_2 UINT64_C(0x0000000000000004) 321 #define CIU_INTX_EN0_WORKQ_1 UINT64_C(0x0000000000000002) 322 #define CIU_INTX_EN0_WORKQ_0 UINT64_C(0x0000000000000001) 323 324 #define CIU_INTX_EN1_XXX_63_1 UINT64_C(0xfffffffffffffffe) 325 #define CIU_INTX_EN1_WDOG UINT64_C(0x0000000000000001) 326 327 #define CIU_TIMX_XXX_63_37 UINT64_C(0xffffffe000000000) 328 #define CIU_TIMX_ONE_SHOT UINT64_C(0x0000001000000000) 329 #define CIU_TIMX_LEN UINT64_C(0x0000000fffffffff) 330 331 #define CIU_WDOGX_XXX_63_46 UINT64_C(0xffffc00000000000) 332 #define CIU_WDOGX_GSTOPEN UINT64_C(0x0000200000000000) 333 #define CIU_WDOGX_DSTOP UINT64_C(0x0000100000000000) 334 #define CIU_WDOGX_CNT UINT64_C(0x00000ffffff00000) 335 #define CIU_WDOGX_LEN UINT64_C(0x00000000000ffff0) 336 #define CIU_WDOGX_STATE UINT64_C(0x000000000000000c) 337 #define CIU_WDOGX_MODE UINT64_C(0x0000000000000003) 338 339 #define CIU_PP_POKEX_XXX_63_0 UINT64_C(0xffffffffffffffff) 340 341 #define CIU_MBOX_SETX_XXX_63_32 UINT64_C(0xffffffff00000000) 342 #define CIU_MBOX_SETX_SET UINT64_C(0x00000000ffffffff) 343 344 #define CIU_MBOX_CLRX_XXX_63_32 UINT64_C(0xffffffff00000000) 345 #define CIU_MBOX_CLRX_CLR UINT64_C(0x00000000ffffffff) 346 347 #define CIU_PP_RST_XXX_63_1 UINT64_C(0xfffffffffffffffe) 348 #define CIU_PP_RST_RST0 UINT64_C(0x0000000000000001) 349 350 #define CIU_PP_DBG_XXX_63_1 UINT64_C(0xfffffffffffffffe) 351 #define CIU_PP_DBG_PPDBG UINT64_C(0x0000000000000001) 352 353 #define CIU_GSTOP_XXX_63_1 UINT64_C(0xfffffffffffffffe) 354 #define CIU_GSTOP_GSTOP UINT64_C(0x0000000000000001) 355 356 #define CIU_NMI_XXX_63_1 UINT64_C(0xfffffffffffffffe) 357 #define CIU_NMI_NMI UINT64_C(0x0000000000000001) 358 359 #define CIU_DINT_XXX_63_1 UINT64_C(0xfffffffffffffffe) 360 #define CIU_DINT_DINT UINT64_C(0x0000000000000001) 361 362 #define CIU_FUSE_XXX_63_1 UINT64_C(0xfffffffffffffffe) 363 #define CIU_FUSE_FUSE UINT64_C(0x0000000000000001) 364 365 #define CIU_BIST_XXX_63_4 UINT64_C(0xfffffffffffffff0) 366 #define CIU_BIST_BIST UINT64_C(0x000000000000000f) 367 368 #define CIU_SOFT_BIST_XXX_63_1 UINT64_C(0xfffffffffffffffe) 369 #define CIU_SOFT_BIST_SOFT_BIST UINT64_C(0x0000000000000001) 370 371 #define CIU_SOFT_RST_XXX_63_1 UINT64_C(0xfffffffffffffffe) 372 #define CIU_SOFT_RST_SOFT_RST UINT64_C(0x0000000000000001) 373 374 #define CIU_SOFT_PRST_XXX_63_1 UINT64_C(0xfffffffffffffff8) 375 #define CIU_SOFT_PRST_HOST64 UINT64_C(0x0000000000000004) 376 #define CIU_SOFT_PRST_NPI UINT64_C(0x0000000000000002) 377 #define CIU_SOFT_PRST_SOFT_PRST UINT64_C(0x0000000000000001) 378 379 #define CIU_PCI_INTA_XXX_63_2 UINT64_C(0xfffffffffffffffc) 380 #define CIU_PCI_INTA_INT UINT64_C(0x0000000000000003) 381 382 /* -- snprintb(9) */ 383 384 #define CIU_INTX_SUM0_BITS \ 385 "\177" /* new format */ \ 386 "\020" /* hex display */ \ 387 "\020" /* %016x format */ \ 388 "b\x3a" "MPI\0" \ 389 "b\x39" "PCM\0" \ 390 "b\x38" "USB\0" \ 391 "b\x37" "TIMER_3\0" \ 392 "b\x36" "TIMER_2\0" \ 393 "b\x35" "TIMER_1\0" \ 394 "b\x34" "TIMER_0\0" \ 395 "f\x34\x04" "TIMER\0" \ 396 "b\x32" "IPD_DRP\0" \ 397 "b\x30" "GMX_DRP\0" \ 398 "b\x2f" "TRACE\0" \ 399 "b\x2e" "RML\0" \ 400 "b\x2d" "TWSI\0" \ 401 "b\x2c" "WDOG_SUM\0" \ 402 "b\x2b" "PCI_MSI_63_48\0" \ 403 "b\x2a" "PCI_MSI_47_32\0" \ 404 "b\x29" "PCI_MSI_31_16\0" \ 405 "b\x28" "PCI_MSI_15_0\0" \ 406 "f\x28\x04" "PCI_MSI\0" \ 407 "b\x27" "PCI_INT_D\0" \ 408 "b\x26" "PCI_INT_C\0" \ 409 "b\x25" "PCI_INT_B\0" \ 410 "f\x24\x04" "PCI_INT\0" \ 411 "b\x24" "PCI_INT_A\0" \ 412 "b\x23" "UART_1\0" \ 413 "b\x22" "UART_0\0" \ 414 "f\x22\x02" "UART\0" \ 415 "b\x21" "MBOX_31_16\0" \ 416 "f\x20\x02" "MBOX\0" \ 417 "b\x20" "MBOX_15_0\0" \ 418 "b\x1f" "GPIO_15\0" \ 419 "b\x1e" "GPIO_14\0" \ 420 "b\x1d" "GPIO_13\0" \ 421 "b\x1c" "GPIO_12\0" \ 422 "b\x1b" "GPIO_11\0" \ 423 "b\x1a" "GPIO_10\0" \ 424 "b\x19" "GPIO_9\0" \ 425 "b\x18" "GPIO_8\0" \ 426 "b\x17" "GPIO_7\0" \ 427 "b\x16" "GPIO_6\0" \ 428 "b\x15" "GPIO_5\0" \ 429 "b\x14" "GPIO_4\0" \ 430 "b\x13" "GPIO_3\0" \ 431 "b\x12" "GPIO_2\0" \ 432 "b\x11" "GPIO_1\0" \ 433 "b\x10" "GPIO_0\0" \ 434 "f\x10\x10" "GPIO\0" \ 435 "b\x0f" "WORKQ_15\0" \ 436 "b\x0e" "WORKQ_14\0" \ 437 "b\x0d" "WORKQ_13\0" \ 438 "b\x0c" "WORKQ_12\0" \ 439 "b\x0b" "WORKQ_11\0" \ 440 "b\x0a" "WORKQ_10\0" \ 441 "b\x09" "WORKQ_9\0" \ 442 "b\x08" "WORKQ_8\0" \ 443 "b\x07" "WORKQ_7\0" \ 444 "b\x06" "WORKQ_6\0" \ 445 "b\x05" "WORKQ_5\0" \ 446 "b\x04" "WORKQ_4\0" \ 447 "b\x03" "WORKQ_3\0" \ 448 "b\x02" "WORKQ_2\0" \ 449 "b\x01" "WORKQ_1\0" \ 450 "b\x00" "WORKQ_0\0" \ 451 "f\x00\x10" "WORKQ\0" 452 #define CIU_INT0_SUM0_BITS CIU_INTX_SUM0_BITS 453 #define CIU_INT1_SUM0_BITS CIU_INTX_SUM0_BITS 454 #define CIU_INT2_SUM0_BITS CIU_INTX_SUM0_BITS 455 #define CIU_INT3_SUM0_BITS CIU_INTX_SUM0_BITS 456 #define CIU_INT32_SUM0_BITS CIU_INTX_SUM0_BITS 457 458 #define CIU_INT_SUM1_BITS \ 459 "\177" /* new format */ \ 460 "\020" /* hex display */ \ 461 "\020" /* %016x format */ \ 462 "b\x00" "WDOG\0" 463 464 #define CIU_INTX_EN0_BITS \ 465 "\177" /* new format */ \ 466 "\020" /* hex display */ \ 467 "\020" /* %016x format */ \ 468 "b\x3a" "MPI\0" \ 469 "b\x39" "PCM\0" \ 470 "b\x38" "USB\0" \ 471 "b\x37" "TIMER_3\0" \ 472 "b\x36" "TIMER_2\0" \ 473 "b\x35" "TIMER_1\0" \ 474 "b\x34" "TIMER_0\0" \ 475 "f\x34\x04" "TIMER\0" \ 476 "b\x32" "IPD_DRP\0" \ 477 "b\x30" "GMX_DRP\0" \ 478 "b\x2f" "TRACE\0" \ 479 "b\x2e" "RML\0" \ 480 "b\x2d" "TWSI\0" \ 481 "b\x2c" "WDOG_SUM\0" \ 482 "b\x2b" "PCI_MSI_63_48\0" \ 483 "b\x2a" "PCI_MSI_47_32\0" \ 484 "b\x29" "PCI_MSI_31_16\0" \ 485 "b\x28" "PCI_MSI_15_0\0" \ 486 "f\x28\x04" "PCI_MSI\0" \ 487 "b\x27" "PCI_INT_D\0" \ 488 "b\x26" "PCI_INT_C\0" \ 489 "b\x25" "PCI_INT_B\0" \ 490 "f\x24\x04" "PCI_INT\0" \ 491 "b\x24" "PCI_INT_A\0" \ 492 "b\x23" "UART_1\0" \ 493 "b\x22" "UART_0\0" \ 494 "f\x22\x02" "UART\0" \ 495 "b\x21" "MBOX_31_16\0" \ 496 "f\x20\x02" "MBOX\0" \ 497 "b\x20" "MBOX_15_0\0" \ 498 "b\x1f" "GPIO_15\0" \ 499 "b\x1e" "GPIO_14\0" \ 500 "b\x1d" "GPIO_13\0" \ 501 "b\x1c" "GPIO_12\0" \ 502 "b\x1b" "GPIO_11\0" \ 503 "b\x1a" "GPIO_10\0" \ 504 "b\x19" "GPIO_9\0" \ 505 "b\x18" "GPIO_8\0" \ 506 "b\x17" "GPIO_7\0" \ 507 "b\x16" "GPIO_6\0" \ 508 "b\x15" "GPIO_5\0" \ 509 "b\x14" "GPIO_4\0" \ 510 "b\x13" "GPIO_3\0" \ 511 "b\x12" "GPIO_2\0" \ 512 "b\x11" "GPIO_1\0" \ 513 "b\x10" "GPIO_0\0" \ 514 "f\x10\x10" "GPIO\0" \ 515 "b\x0f" "WORKQ_15\0" \ 516 "b\x0e" "WORKQ_14\0" \ 517 "b\x0d" "WORKQ_13\0" \ 518 "b\x0c" "WORKQ_12\0" \ 519 "b\x0b" "WORKQ_11\0" \ 520 "b\x0a" "WORKQ_10\0" \ 521 "b\x09" "WORKQ_9\0" \ 522 "b\x08" "WORKQ_8\0" \ 523 "b\x07" "WORKQ_7\0" \ 524 "b\x06" "WORKQ_6\0" \ 525 "b\x05" "WORKQ_5\0" \ 526 "b\x04" "WORKQ_4\0" \ 527 "b\x03" "WORKQ_3\0" \ 528 "b\x02" "WORKQ_2\0" \ 529 "b\x01" "WORKQ_1\0" \ 530 "b\x00" "WORKQ_0\0" \ 531 "f\x00\x10" "WORKQ\0" 532 #define CIU_INT0_EN0_BITS CIU_INTX_EN0_BITS 533 #define CIU_INT1_EN0_BITS CIU_INTX_EN0_BITS 534 #define CIU_INT2_EN0_BITS CIU_INTX_EN0_BITS 535 #define CIU_INT3_EN0_BITS CIU_INTX_EN0_BITS 536 #define CIU_INT32_EN0_BITS CIU_INTX_EN0_BITS 537 538 #define CIU_INTX_EN1_BITS \ 539 "\177" /* new format */ \ 540 "\020" /* hex display */ \ 541 "\020" /* %016x format */ \ 542 "b\x00" "WDOG\0" 543 #define CIU_INT0_EN1_BITS CIU_INTX_EN1_BITS 544 #define CIU_INT1_EN1_BITS CIU_INTX_EN1_BITS 545 #define CIU_INT2_EN1_BITS CIU_INTX_EN1_BITS 546 #define CIU_INT3_EN1_BITS CIU_INTX_EN1_BITS 547 #define CIU_INT32_EN1_BITS CIU_INTX_EN1_BITS 548 549 #define CIU_TIMX_BITS \ 550 "\177" /* new format */ \ 551 "\020" /* hex display */ \ 552 "\020" /* %016x format */ \ 553 "b\x24" "ONE_SHOT\0" \ 554 "f\x00\x24" "LEN\0" 555 #define CIU_TIM0_BITS CIU_TIMX_BITS 556 #define CIU_TIM1_BITS CIU_TIMX_BITS 557 #define CIU_TIM2_BITS CIU_TIMX_BITS 558 #define CIU_TIM3_BITS CIU_TIMX_BITS 559 #define CIU_TIM32_BITS CIU_TIMX_BITS 560 561 #define CIU_WDOGX_BITS \ 562 "\177" /* new format */ \ 563 "\020" /* hex display */ \ 564 "\020" /* %016x format */ \ 565 "b\x2d" "GSTOPEN\0" \ 566 "b\x2c" "DSTOP\0" \ 567 "f\x14\x18" "CNT\0" \ 568 "f\x04\x10" "LEN\0" \ 569 "f\x02\x02" "STATE\0" \ 570 "f\x00\x02" "MODE\0" 571 #define CIU_WDOG0_BITS CIU_WDOGX_BITS 572 #define CIU_WDOG1_BITS CIU_WDOGX_BITS 573 574 #if 0 575 #define CIU_PP_POKEX_BITS \ 576 "\177" /* new format */ \ 577 "\020" /* hex display */ \ 578 "\020" /* %016x format */ \ 579 580 #define CIU_PP_POKE0_BITS CIU_PP_POKEX_BITS 581 #define CIU_PP_POKE1_BITS CIU_PP_POKEX_BITS 582 #endif 583 584 #define CIU_MBOX_SETX_BITS \ 585 "\177" /* new format */ \ 586 "\020" /* hex display */ \ 587 "\020" /* %016x format */ \ 588 "f\x00\x20" "SET\0" 589 #define CIU_MBOX_SET0_BITS CIU_MBOX_SETX_BITS 590 #define CIU_MBOX_SET1_BITS CIU_MBOX_SETX_BITS 591 592 #define CIU_MBOX_CLRX_BITS \ 593 "\177" /* new format */ \ 594 "\020" /* hex display */ \ 595 "\020" /* %016x format */ \ 596 "f\x00\x20" "CLR\0" 597 #define CIU_MBOX_CLR0_BITS CIU_MBOX_CLRX_BITS 598 #define CIU_MBOX_CLR1_BITS CIU_MBOX_CLRX_BITS 599 600 #define CIU_PP_RST_BITS \ 601 "\177" /* new format */ \ 602 "\020" /* hex display */ \ 603 "\020" /* %016x format */ \ 604 "b\x00" "RST0\0" 605 606 #define CIU_PP_DBG_BITS \ 607 "\177" /* new format */ \ 608 "\020" /* hex display */ \ 609 "\020" /* %016x format */ \ 610 "b\x00" "PPDBG\0" 611 612 #define CIU_GSTOP_BITS \ 613 "\177" /* new format */ \ 614 "\020" /* hex display */ \ 615 "\020" /* %016x format */ \ 616 "b\x00" "GSTOP\0" 617 618 #define CIU_NMI_BITS \ 619 "\177" /* new format */ \ 620 "\020" /* hex display */ \ 621 "\020" /* %016x format */ \ 622 "b\x00" "NMI\0" 623 624 #define CIU_DINT_BITS \ 625 "\177" /* new format */ \ 626 "\020" /* hex display */ \ 627 "\020" /* %016x format */ \ 628 "b\x00" "DINT\0" 629 630 #define CIU_FUSE_BITS \ 631 "\177" /* new format */ \ 632 "\020" /* hex display */ \ 633 "\020" /* %016x format */ \ 634 "b\x00" "FUSE\0" 635 636 #define CIU_BIST_BITS \ 637 "\177" /* new format */ \ 638 "\020" /* hex display */ \ 639 "\020" /* %016x format */ \ 640 "f\x00\x04" "BIST\0" 641 642 #define CIU_SOFT_BIST_BITS \ 643 "\177" /* new format */ \ 644 "\020" /* hex display */ \ 645 "\020" /* %016x format */ \ 646 "b\x00" "SOFT_BIST\0" 647 648 #define CIU_SOFT_RST_BITS \ 649 "\177" /* new format */ \ 650 "\020" /* hex display */ \ 651 "\020" /* %016x format */ \ 652 "b\x00" "SOFT_RST\0" 653 654 #define CIU_SOFT_PRST_BITS \ 655 "\177" /* new format */ \ 656 "\020" /* hex display */ \ 657 "\020" /* %016x format */ \ 658 "b\x02" "HOST64\0" \ 659 "b\x01" "NPI\0" \ 660 "b\x00" "SOFT_PRST\0" 661 662 #define CIU_PCI_INTA_BITS \ 663 "\177" /* new format */ \ 664 "\020" /* hex display */ \ 665 "\020" /* %016x format */ \ 666 "f\x00\x02" "INT\0" 667 668 #endif /* _OCTEON_CIUREG_H_ */ 669
Indexes created Mon Sep 29 21:09:56 GMT 2025