Cross Reference: /src/sys/arch/mips/cavium/dev/octeon

History log of /src/sys/arch/mips/cavium/dev/octeon_corereg.h
Revision	Date	Author	Comments
1.5	04-Aug-2020	simonb	Add some CvmCtl bits from newer cnMIPS cores.
1.4	26-Jul-2020	simonb	Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core specific regs.
1.3	22-Jun-2020	simonb	Remove unused snprintb format strings.
1.2	01-Jun-2015	matt	branches: 1.2.2; 1.2.18; Rework cavium support in preparation for MULTIPROCESSOR support
1.1	29-Apr-2015	hikaru	Initial import of Cavium Octeon and Octeon Plus SoC and specifically Ubiquiti Networks EdgeRouter LITE support. Currently the ethernet and uart are worked. This support was contributed by Internet Initiative Japan Inc.
1.2.18.2	03-Dec-2017	jdolecek	update from HEAD
1.2.18.1	01-Jun-2015	jdolecek	file octeon_corereg.h was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000
1.2.2.2	06-Jun-2015	skrll	Sync with HEAD
1.2.2.1	01-Jun-2015	skrll	file octeon_corereg.h was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000

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