1 1.5 simonb /* $NetBSD: octeon_corereg.h,v 1.5 2020/08/04 01:59:46 simonb Exp $ */ 2 1.1 hikaru 3 1.1 hikaru /* 4 1.1 hikaru * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 1.1 hikaru * All rights reserved. 6 1.1 hikaru * 7 1.1 hikaru * Redistribution and use in source and binary forms, with or without 8 1.1 hikaru * modification, are permitted provided that the following conditions 9 1.1 hikaru * are met: 10 1.1 hikaru * 1. Redistributions of source code must retain the above copyright 11 1.1 hikaru * notice, this list of conditions and the following disclaimer. 12 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 hikaru * notice, this list of conditions and the following disclaimer in the 14 1.1 hikaru * documentation and/or other materials provided with the distribution. 15 1.1 hikaru * 16 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 hikaru * SUCH DAMAGE. 27 1.1 hikaru */ 28 1.1 hikaru 29 1.1 hikaru #ifndef _OCTEON_COREREG_H_ 30 1.1 hikaru #define _OCTEON_COREREG_H_ 31 1.1 hikaru 32 1.1 hikaru /* ---- register bits */ 33 1.1 hikaru 34 1.1 hikaru /* 35 1.4 simonb * Cavium Networks-Specific Coprocessor 0 Registers 36 1.1 hikaru */ 37 1.1 hikaru 38 1.1 hikaru /* CacheErr (Icache) */ 39 1.1 hikaru 40 1.1 hikaru #define CP0_CACHEERRI_XXX_63_55 UINT64_C(0xff80000000000000) 41 1.1 hikaru #define CP0_CACHEERRI_BADCOLF UINT64_C(0x007f000000000000) 42 1.1 hikaru #define CP0_CACHEERRI_XXX_47 UINT64_C(0x0000800000000000) 43 1.1 hikaru #define CP0_CACHEERRI_BADCOL UINT64_C(0x00007f0000000000) 44 1.1 hikaru #define CP0_CACHEERRI_XXX_39_37 UINT64_C(0x000000e000000000) 45 1.1 hikaru #define CP0_CACHEERRI_LRUFAIL UINT64_C(0x0000001000000000) 46 1.1 hikaru #define CP0_CACHEERRI_AESFAIL UINT64_C(0x0000000800000000) 47 1.1 hikaru #define CP0_CACHEERRI_HSHFAIL UINT64_C(0x0000000400000000) 48 1.1 hikaru #define CP0_CACHEERRI_BHTBROKE UINT64_C(0x0000000200000000) 49 1.1 hikaru #define CP0_CACHEERRI_ICBROKE UINT64_C(0x0000000100000000) 50 1.1 hikaru #define CP0_CACHEERRI_XXX_31_15 UINT64_C(0x00000000ffff8000) 51 1.1 hikaru #define CP0_CACHEERRI_QW UINT64_C(0x0000000000006000) 52 1.1 hikaru #define CP0_CACHEERRI_ROW UINT64_C(0x0000000000001800) 53 1.1 hikaru #define CP0_CACHEERRI_SET UINT64_C(0x00000000000007e0) 54 1.1 hikaru #define CP0_CACHEERRI_WAY UINT64_C(0x0000000000000018) 55 1.1 hikaru #define CP0_CACHEERRI_XXX_2_1 UINT64_C(0x0000000000000006) 56 1.1 hikaru #define CP0_CACHEERRI_DPERR UINT64_C(0x0000000000000001) 57 1.1 hikaru 58 1.1 hikaru /* CacheErr (Dcache) */ 59 1.1 hikaru 60 1.1 hikaru #define CP0_CACHEERRD_XXX_63_13 UINT64_C(0xffffffffffffe000) 61 1.1 hikaru #define CP0_CACHEERRD_SET UINT64_C(0x0000000000001f80) 62 1.1 hikaru #define CP0_CACHEERRD_VA63 UINT64_C(0x0000000000000078) 63 1.1 hikaru #define CP0_CACHEERRD_XXX_2_1 UINT64_C(0x0000000000000006) 64 1.1 hikaru #define CP0_CACHEERRD_PERR UINT64_C(0x0000000000000001) 65 1.1 hikaru 66 1.1 hikaru /* TagLo Register (Icache) */ 67 1.1 hikaru 68 1.1 hikaru #define CP0_TAGLOI_R UINT64_C(0xc000000000000000) 69 1.1 hikaru #define CP0_TAGLOI_XXX_61_60 UINT64_C(0x3000000000000000) 70 1.1 hikaru #define CP0_TAGLOI_ASID UINT64_C(0x0f00000000000000) 71 1.1 hikaru #define CP0_TAGLOI_XXX_51_49 UINT64_C(0x00f0000000000000) 72 1.1 hikaru #define CP0_TAGLOI_TAG UINT64_C(0x000fffffffffe000) 73 1.1 hikaru #define CP0_TAGLOI_INDEX UINT64_C(0x0000000000001f80) 74 1.1 hikaru #define CP0_TAGLOI_XXX_6_2 UINT64_C(0x000000000000007c) 75 1.1 hikaru #define CP0_TAGLOI_G UINT64_C(0x0000000000000002) 76 1.1 hikaru #define CP0_TAGLOI_VALID UINT64_C(0x0000000000000001) 77 1.1 hikaru 78 1.1 hikaru /* TagLo Register (Dcache) */ 79 1.1 hikaru 80 1.1 hikaru #define CP0_TAGLOD_R UINT64_C(0xc000000000000000) 81 1.1 hikaru #define CP0_TAGLOD_XXX_61_60 UINT64_C(0x3000000000000000) 82 1.1 hikaru #define CP0_TAGLOD_ASID UINT64_C(0x0f00000000000000) 83 1.1 hikaru #define CP0_TAGLOD_XXX_51_49 UINT64_C(0x00f0000000000000) 84 1.1 hikaru #define CP0_TAGLOD_TAG UINT64_C(0x000fffffffffff80) 85 1.1 hikaru #define CP0_TAGLOD_XXX_6_2 UINT64_C(0x000000000000007c) 86 1.1 hikaru #define CP0_TAGLOD_G UINT64_C(0x0000000000000002) 87 1.1 hikaru #define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001) 88 1.1 hikaru 89 1.1 hikaru /* CvmCtl Register */ 90 1.5 simonb /* CVMCTL_STEPRATE to CVMCTL_TLBBRFTDIS are available on cnMIPS III cores */ 91 1.1 hikaru 92 1.5 simonb #define CP0_CVMCTL_XXX_63_43 UINT64_C(0xfffff80000000000) 93 1.5 simonb #define CP0_CVMCTL_STEPRATE UINT64_C(0x0000078000000000) 94 1.5 simonb #define CP0_CVMCTL_ZUC UINT64_C(0x0000004000000000) 95 1.5 simonb #define CP0_CVMCTL_CAMELLIA UINT64_C(0x0000002000000000) 96 1.5 simonb #define CP0_CVMCTL_USEMAK UINT64_C(0x0000001000000000) 97 1.5 simonb #define CP0_CVMCTL_SMS4 UINT64_C(0x0000000800000000) 98 1.5 simonb #define CP0_CVMCTL_DISABLEPAUSE UINT64_C(0x0000000400000000) 99 1.5 simonb #define CP0_CVMCTL_SNOW3G UINT64_C(0x0000000200000000) 100 1.5 simonb #define CP0_CVMCTL_TLBBRFTDIS UINT64_C(0x0000000100000000) 101 1.1 hikaru #define CP0_CVMCTL_FUSE_STARTBIT UINT64_C(0x0000000080000000) 102 1.2 matt #define CP0_CVMCTL_XXX_30 UINT64_C(0x0000000040000000) 103 1.2 matt #define CP0_CVMCTL_KASUMI UINT64_C(0x0000000020000000) 104 1.1 hikaru #define CP0_CVMCTL_NODFA_CP21 UINT64_C(0x0000000010000000) 105 1.1 hikaru #define CP0_CVMCTL_NOMUL UINT64_C(0x0000000008000000) 106 1.1 hikaru #define CP0_CVMCTL_NOCRYPTO UINT64_C(0x0000000004000000) 107 1.1 hikaru #define CP0_CVMCTL_RST_SHT UINT64_C(0x0000000002000000) 108 1.1 hikaru #define CP0_CVMCTL_BIST_DIS UINT64_C(0x0000000001000000) 109 1.1 hikaru #define CP0_CVMCTL_DISSETPRED UINT64_C(0x0000000000800000) 110 1.1 hikaru #define CP0_CVMCTL_DISJRPRED UINT64_C(0x0000000000400000) 111 1.1 hikaru #define CP0_CVMCTL_DISICACHE UINT64_C(0x0000000000200000) 112 1.1 hikaru #define CP0_CVMCTL_DISWAIT UINT64_C(0x0000000000100000) 113 1.1 hikaru #define CP0_CVMCTL_DEFET UINT64_C(0x0000000000080000) 114 1.1 hikaru #define CP0_CVMCTL_DISCO UINT64_C(0x0000000000040000) 115 1.1 hikaru #define CP0_CVMCTL_DISCE UINT64_C(0x0000000000020000) 116 1.1 hikaru #define CP0_CVMCTL_DDCLK UINT64_C(0x0000000000010000) 117 1.1 hikaru #define CP0_CVMCTL_DCICLK UINT64_C(0x0000000000008000) 118 1.1 hikaru #define CP0_CVMCTL_REPUN UINT64_C(0x0000000000004000) 119 1.1 hikaru #define CP0_CVMCTL_IPREF UINT64_C(0x0000000000002000) 120 1.1 hikaru #define CP0_CVMCTL_USEUN UINT64_C(0x0000000000001000) 121 1.1 hikaru #define CP0_CVMCTL_DISIOCACHE UINT64_C(0x0000000000000800) 122 1.1 hikaru #define CP0_CVMCTL_IRAND UINT64_C(0x0000000000000400) 123 1.1 hikaru #define CP0_CVMCTL_IPPCI UINT64_C(0x0000000000000380) 124 1.1 hikaru #define CP0_CVMCTL_IPTI UINT64_C(0x0000000000000070) 125 1.1 hikaru #define CP0_CVMCTL_XXX_3_2 UINT64_C(0x000000000000000c) 126 1.1 hikaru #define CP0_CVMCTL_LE UINT64_C(0x0000000000000002) 127 1.1 hikaru #define CP0_CVMCTL_USELY UINT64_C(0x0000000000000001) 128 1.1 hikaru 129 1.1 hikaru /* CvmMemCtl Register */ 130 1.1 hikaru 131 1.1 hikaru #define CP0_CVMMEMCTL_TLBBIST UINT64_C(0x8000000000000000) 132 1.1 hikaru #define CP0_CVMMEMCTL_L1CBIST UINT64_C(0x4000000000000000) 133 1.1 hikaru #define CP0_CVMMEMCTL_L1DBIST UINT64_C(0x2000000000000000) 134 1.1 hikaru #define CP0_CVMMEMCTL_DCMBIST UINT64_C(0x1000000000000000) 135 1.1 hikaru #define CP0_CVMMEMCTL_PTGBIST UINT64_C(0x0800000000000000) 136 1.1 hikaru #define CP0_CVMMEMCTL_WBFBIST UINT64_C(0x0400000000000000) 137 1.1 hikaru #define CP0_CVMMEMCTL_XXX_57_36 UINT64_C(0x03fffff000000000) 138 1.1 hikaru #define CP0_CVMMEMCTL_DISMARKWBLONGTO UINT64_C(0x0000000800000000) 139 1.1 hikaru #define CP0_CVMMEMCTL_DISMRGCLRWBTO UINT64_C(0x0000000400000000) 140 1.1 hikaru #define CP0_CVMMEMCTL_IOBDMASCRMSB UINT64_C(0x0000000300000000) 141 1.1 hikaru #define CP0_CVMMEMCTL_SYNCWSMARKED UINT64_C(0x0000000080000000) 142 1.1 hikaru #define CP0_CVMMEMCTL_DISSYNCWS UINT64_C(0x0000000040000000) 143 1.1 hikaru #define CP0_CVMMEMCTL_DISWBFST UINT64_C(0x0000000020000000) 144 1.1 hikaru #define CP0_CVMMEMCTL_XKMEMENAS UINT64_C(0x0000000010000000) 145 1.1 hikaru #define CP0_CVMMEMCTL_XKMEMENAU UINT64_C(0x0000000008000000) 146 1.1 hikaru #define CP0_CVMMEMCTL_XKIOENAS UINT64_C(0x0000000004000000) 147 1.1 hikaru #define CP0_CVMMEMCTL_XKIOENAU UINT64_C(0x0000000002000000) 148 1.1 hikaru #define CP0_CVMMEMCTL_ALLSYNCW UINT64_C(0x0000000001000000) 149 1.1 hikaru #define CP0_CVMMEMCTL_NOMERGE UINT64_C(0x0000000000800000) 150 1.1 hikaru #define CP0_CVMMEMCTL_DIDTTO UINT64_C(0x0000000000600000) 151 1.1 hikaru #define CP0_CVMMEMCTL_CSRCLKALWYS UINT64_C(0x0000000000100000) 152 1.1 hikaru #define CP0_CVMMEMCTL_MCLKALWYS UINT64_C(0x0000000000080000) 153 1.1 hikaru #define CP0_CVMMEMCTL_WBFLTIME UINT64_C(0x0000000000070000) 154 1.1 hikaru #define CP0_CVMMEMCTL_ISTRNOL2 UINT64_C(0x0000000000008000) 155 1.1 hikaru #define CP0_CVMMEMCTL_WBTHRESH UINT64_C(0x0000000000007800) 156 1.1 hikaru #define CP0_CVMMEMCTL_XXX_10_9 UINT64_C(0x0000000000000600) 157 1.1 hikaru #define CP0_CVMMEMCTL_CVMSEGENAK UINT64_C(0x0000000000000100) 158 1.1 hikaru #define CP0_CVMMEMCTL_CVMSEGENAS UINT64_C(0x0000000000000080) 159 1.1 hikaru #define CP0_CVMMEMCTL_CVMSEGENAU UINT64_C(0x0000000000000040) 160 1.1 hikaru #define CP0_CVMMEMCTL_LMEMSZ UINT64_C(0x000000000000003f) 161 1.1 hikaru 162 1.1 hikaru /* CvmCount Register */ 163 1.1 hikaru 164 1.1 hikaru /* Multi-Core Debug Register */ 165 1.1 hikaru 166 1.1 hikaru #define CP0_MCD_XXX_63_17 UINT64_C(0xfffffffffffe0000) 167 1.1 hikaru #define CP0_MCD_DEXCC UINT64_C(0x0000000000010000) 168 1.1 hikaru #define CP0_MCD_CGSTP UINT64_C(0x0000000000008000) 169 1.1 hikaru #define CP0_MCD_CVGSTP UINT64_C(0x0000000000004000) 170 1.1 hikaru #define CP0_MCD_CVDM UINT64_C(0x0000000000002000) 171 1.1 hikaru #define CP0_MCD_GSDB UINT64_C(0x0000000000001000) 172 1.1 hikaru #define CP0_MCD_XXX_11 UINT64_C(0x0000000000000800) 173 1.1 hikaru #define CP0_MCD_MSKM2 UINT64_C(0x0000000000000400) 174 1.1 hikaru #define CP0_MCD_MSKM1 UINT64_C(0x0000000000000200) 175 1.1 hikaru #define CP0_MCD_MMC0 UINT64_C(0x0000000000000100) 176 1.1 hikaru #define CP0_MCD_XXX_7 UINT64_C(0x0000000000000080) 177 1.1 hikaru #define CP0_MCD_PLS2 UINT64_C(0x0000000000000040) 178 1.1 hikaru #define CP0_MCD_PLS1 UINT64_C(0x0000000000000020) 179 1.1 hikaru #define CP0_MCD_PLS0 UINT64_C(0x0000000000000010) 180 1.1 hikaru #define CP0_MCD_XXX_3 UINT64_C(0x0000000000000008) 181 1.1 hikaru #define CP0_MCD_MCD2 UINT64_C(0x0000000000000004) 182 1.1 hikaru #define CP0_MCD_MCD1 UINT64_C(0x0000000000000002) 183 1.1 hikaru #define CP0_MCD_MCD0 UINT64_C(0x0000000000000001) 184 1.1 hikaru 185 1.1 hikaru /* ---- operations */ 186 1.1 hikaru 187 1.1 hikaru /* 188 1.1 hikaru * OCTEON Configuration and Status Registers (CSRs) 189 1.1 hikaru */ 190 1.1 hikaru 191 1.1 hikaru #define CSR_COP0 /* Core coprosessor 0 registers */ 192 1.1 hikaru #define CSR_COP2 /* Core coprosessor 2 registers */ 193 1.1 hikaru #define CSR_COREEJTAG /* Core EJTAG registers */ 194 1.1 hikaru #define CSR_COREEJTAGTAP /* Core EJTAG TAP registers */ 195 1.1 hikaru #define CSR_NCB /* NCB registers */ 196 1.1 hikaru #define CSR_RSL /* RSL registers */ 197 1.1 hikaru #define CSR_PCICONFIG /* PCICONFIG registers */ 198 1.1 hikaru #define CSR_PCI /* PCI registers */ 199 1.1 hikaru #define CSR_PCINCB /* PCI_NCB registers */ 200 1.1 hikaru #define CSR_JTAGTAP /* JTAG TAP registers */ 201 1.1 hikaru #define CSR_TWSICORE /* TWSI Core registers */ 202 1.1 hikaru 203 1.1 hikaru /* XXX */ 204 1.1 hikaru 205 1.1 hikaru #endif /* _OCTEON_COREREG_H_ */ 206