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History log of /src/sys/arch/mips/cavium/dev/octeon_smi.c
RevisionDateAuthorComments
 1.9  29-Sep-2022  skrll Remove unnecessary include of <sys/malloc.h>.
 1.8  29-Sep-2022  skrll Trailing whitespace
 1.7  27-Jan-2021  thorpej Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.
 1.6  16-Jul-2020  jmcneill branches: 1.6.2;
FDT support for Cavium OCTEON MIPS SoCs. WIP.
 1.5  23-Jun-2020  simonb Redo cnmac attachments - cnmacM @ gmxN @ pip0 @ iobus
 1.4  18-Jun-2020  simonb General code cleanup:
- use generic macros for building IO and IOBDMA addresses instead
of many different variations of the same theme.
- use #define's for CVMSEG addresses instead of magic numbers.
- use __BIT/__BITS/__SHIFTIN/__SHIFTOUT in most places, instead of
foo_SHIFT defines or (worse) shifting by magic numbers.

No functional changes.
 1.3  31-May-2020  simonb Rename all Cavium Octeon device driver functions, structs etc from
"octeon_foo" to "octfoo", except "octeon_eth" becomes "cnmac".
 1.2  22-Jan-2019  msaitoh Change MII PHY read/write API from:

int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:

int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);

Now we can test if a read/write operation failed or not by the return value.

In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.

Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:

arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c


Tested with the following device:

axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)

Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url

Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
 1.1  29-Apr-2015  hikaru branches: 1.1.2; 1.1.18; 1.1.20; 1.1.22;
Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.1.22.1  10-Jun-2019  christos Sync with HEAD
 1.1.20.1  26-Jan-2019  pgoyette Sync with HEAD
 1.1.18.2  03-Dec-2017  jdolecek update from HEAD
 1.1.18.1  29-Apr-2015  jdolecek file octeon_smi.c was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000
 1.1.2.2  06-Jun-2015  skrll Sync with HEAD
 1.1.2.1  29-Apr-2015  skrll file octeon_smi.c was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000
 1.6.2.1  03-Apr-2021  thorpej Sync with HEAD.

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