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octeon_smi.c revision 1.1.18.2 
      1 /*	$NetBSD: octeon_smi.c,v 1.1.18.2 2017/12/03 11:36:27 jdolecek Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.1.18.2 2017/12/03 11:36:27 jdolecek Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 #include <sys/malloc.h>
     35 #include <sys/mbuf.h>
     36 #include <mips/locore.h>
     37 #include <mips/cavium/octeonvar.h>
     38 #include <mips/cavium/dev/octeon_fpavar.h>
     39 #include <mips/cavium/dev/octeon_pipreg.h>
     40 #include <mips/cavium/dev/octeon_smireg.h>
     41 #include <mips/cavium/dev/octeon_smivar.h>
     42 
     43 static void		octeon_smi_enable(struct octeon_smi_softc *);
     44 
     45 /* XXX */
     46 void
     47 octeon_smi_init(struct octeon_smi_attach_args *aa,
     48     struct octeon_smi_softc **rsc)
     49 {
     50 	struct octeon_smi_softc *sc;
     51 	int status;
     52 
     53 	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
     54 	if (sc == NULL)
     55 		panic("can't allocate memory: %s", __func__);
     56 
     57 	sc->sc_port = aa->aa_port;
     58 	sc->sc_regt = aa->aa_regt;
     59 
     60 	status = bus_space_map(sc->sc_regt, SMI_BASE, SMI_SIZE, 0,
     61 	    &sc->sc_regh);
     62 	if (status != 0)
     63 		panic("can't map %s space", "smi register");
     64 
     65 	octeon_smi_enable(sc);
     66 
     67 	*rsc = sc;
     68 }
     69 
     70 #define	_SMI_RD8(sc, off) \
     71 	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
     72 #define	_SMI_WR8(sc, off, v) \
     73 	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
     74 
     75 int
     76 octeon_smi_read(struct octeon_smi_softc *sc, int phy_addr, int reg)
     77 {
     78 	uint64_t smi_rd;
     79 	int timo;
     80 
     81 	_SMI_WR8(sc, SMI_CMD_OFFSET, SMI_CMD_PHY_OP |
     82 	    (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
     83 	    (reg << SMI_CMD_REG_ADR_SHIFT));
     84 
     85 	timo = 10000;
     86 	smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
     87 	while (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
     88 		if (timo-- == 0)
     89 			break;
     90 		delay(10);
     91 		smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
     92 	}
     93 	if (ISSET(smi_rd, SMI_RD_DAT_PENDING)) {
     94 		return -1;
     95 	}
     96 
     97 	return ISSET(smi_rd, SMI_RD_DAT_VAL) ? (smi_rd & SMI_RD_DAT_DAT) : 0;
     98 }
     99 
    100 void
    101 octeon_smi_write(struct octeon_smi_softc *sc, int phy_addr, int reg, int value)
    102 {
    103 	uint64_t smi_wr;
    104 	int timo;
    105 
    106 	smi_wr = 0;
    107 	SET(smi_wr, value);
    108 	_SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr);
    109 
    110 	_SMI_WR8(sc, SMI_CMD_OFFSET, (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
    111 	    (reg << SMI_CMD_REG_ADR_SHIFT));
    112 
    113 	timo = 10000;
    114 	smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
    115 	while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
    116 		if (timo-- == 0)
    117 			break;
    118 		delay(10);
    119 		smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
    120 	}
    121 	if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
    122 		/* XXX log */
    123 		printf("ERROR: cnmac_mii_writereg(0x%x, 0x%x, 0x%x) timed out.\n",
    124 		    phy_addr, reg, value);
    125 	}
    126 }
    127 
    128 static void
    129 octeon_smi_enable(struct octeon_smi_softc *sc)
    130 {
    131 	_SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
    132 }
    133 
    134 void
    135 octeon_smi_set_clock(struct octeon_smi_softc *sc, uint64_t clock)
    136 {
    137 	_SMI_WR8(sc, SMI_CLK_OFFSET, clock);
    138 }
    139 
    140