Cross Reference: /src/sys/arch/mips/include/cache

History log of /src/sys/arch/mips/include/cache_tx39.h
Revision	Date	Author	Comments
1.7	11-Jul-2016	matt	Change MIPS to use the common pmap code. Switch to 8KB pages on CPUs with a R4K MMU. Simplify cache code. Merge in most of changes from matt-mips64 branch
1.6	28-Apr-2008	martin	branches: 1.6.18; 1.6.44; 1.6.64; Remove clause 3 and 4 from TNF licenses
1.5	24-Dec-2005	perry	branches: 1.5.74; 1.5.76; 1.5.78; Remove leading __ from __(const\|inline\|signed\|volatile) -- it is obsolete.
1.4	17-Feb-2003	simonb	branches: 1.4.18; No need to protect headers with #ifdef _KERNEL if they're never installed in /usr/include.
1.3	05-Mar-2002	simonb	Clean up #ifdef checks a little.
1.2	14-Nov-2001	thorpej	branches: 1.2.2; 1.2.4; Merge the thorpej-mips-cache branch onto the trunk. This is an overhaul of how caches are handled for NetBSD's MIPS ports.
1.1	24-Oct-2001	thorpej	branches: 1.1.2; file cache_tx39.h was initially added on branch thorpej-mips-cache.
1.1.2.2	30-Oct-2001	uch	add #ifndef _LOCORE
1.1.2.1	24-Oct-2001	thorpej	New style cache operations for TX39-style caches. XXX This is not yet complete.
1.2.4.3	16-Mar-2002	jdolecek	Catch up with -current.
1.2.4.2	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.2.4.1	14-Nov-2001	thorpej	file cache_tx39.h was added on branch kqueue on 2002-01-10 19:46:00 +0000
1.2.2.2	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.2.2.1	14-Nov-2001	nathanw	file cache_tx39.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
1.4.18.1	21-Jun-2006	yamt	sync with head.
1.5.78.1	16-May-2008	yamt	sync with head.
1.5.76.1	18-May-2008	yamt	sync with head.
1.5.74.1	02-Jun-2008	mjf	Sync with HEAD.
1.6.64.1	05-Oct-2016	skrll	Sync with HEAD
1.6.44.1	03-Dec-2017	jdolecek	update from HEAD
1.6.18.1	19-Jan-2012	matt	When running an N32 kernel, run it with 64-bit addresses even though the kernel itself will only use 32-bit addresses. There are exceptions. bus_space_handles are now register_t instead of intptr_t. This allows them to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more KSEG2 space for the kernel to use. The cache range routines (but not index routines) now take a register_t instead of vaddr_t so they can too take a XKPHYS address. This allows the pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding massive icache invalidations. Since "cache" instruction effects are global to all CPUs and their caches, we can use the above to greatly simplify MP page isyncs. If using an O32 kernel with pages outside KSEG0, index ops still need to be performed since there isn't an a quick way of mapping the page.

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