cache_tx39.h revision 1.2
1 /* $NetBSD: cache_tx39.h,v 1.2 2001/11/14 18:26:22 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi; and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cache definitions/operations for TX3900-style caches. 41 * 42 * XXX THIS IS NOT YET COMPLETE. 43 */ 44 45 #define CACHE_TX39_I 0 46 #define CACHE_TX39_D 1 47 48 #define CACHEOP_TX3900_INDEX_INV (0 << 2) /* I */ 49 #define CACHEOP_TX3900_ILRUC (1 << 2) /* I, D */ 50 #define CACHEOP_TX3900_ILCKC (2 << 2) /* D */ 51 #define CACHEOP_TX3900_HIT_INV (4 << 2) /* D */ 52 53 #define CACHEOP_TX3920_INDEX_INV CACHEOP_TX3900_INDEX_INV 54 #define CACHEOP_TX3920_INDEX_WB_INV (0 << 2) /* D */ 55 #define CACHEOP_TX3920_ILRUC CACHEOP_TX3900_ILRUC 56 #define CACHEOP_TX3920_INDEX_LOAD_TAG (3 << 2) /* I, D */ 57 #define CACHEOP_TX3920_HIT_INV (4 << 2) /* I, D */ 58 #define CACHEOP_TX3920_HIT_WB_INV (5 << 2) /* D */ 59 #define CACHEOP_TX3920_HIT_WB (6 << 2) /* D */ 60 #define CACHEOP_TX3920_ISTTAG (7 << 2) /* I, D */ 61 62 #ifdef _KERNEL 63 #ifndef _LOCORE 64 65 /* 66 * cache_tx39_op_line: 67 * 68 * Perform the specified cache operation on a single line. 69 */ 70 #define cache_op_tx39_line(va, op) \ 71 do { \ 72 __asm __volatile( \ 73 ".set noreorder \n\t" \ 74 ".set push \n\t" \ 75 ".set mips3 \n\t" \ 76 "cache %1, 0(%0) \n\t" \ 77 ".set pop \n\t" \ 78 ".set reorder" \ 79 : \ 80 : "r" (va), "i" (op) \ 81 : "memory"); \ 82 } while (/*CONSTCOND*/0) 83 84 /* 85 * cache_tx39_op_32lines_4: 86 * 87 * Perform the specified cache operation on 32 4-byte 88 * cache lines. 89 */ 90 #define cache_tx39_op_32lines_4(va, op) \ 91 do { \ 92 __asm __volatile( \ 93 ".set noreorder \n\t" \ 94 ".set push \n\t" \ 95 ".set mips3 \n\t" \ 96 "cache %1, 0x00(%0); cache %1, 0x04(%0); \n\t" \ 97 "cache %1, 0x08(%0); cache %1, 0x0c(%0); \n\t" \ 98 "cache %1, 0x10(%0); cache %1, 0x14(%0); \n\t" \ 99 "cache %1, 0x18(%0); cache %1, 0x1c(%0); \n\t" \ 100 "cache %1, 0x20(%0); cache %1, 0x24(%0); \n\t" \ 101 "cache %1, 0x28(%0); cache %1, 0x2c(%0); \n\t" \ 102 "cache %1, 0x30(%0); cache %1, 0x34(%0); \n\t" \ 103 "cache %1, 0x38(%0); cache %1, 0x3c(%0); \n\t" \ 104 "cache %1, 0x40(%0); cache %1, 0x44(%0); \n\t" \ 105 "cache %1, 0x48(%0); cache %1, 0x4c(%0); \n\t" \ 106 "cache %1, 0x50(%0); cache %1, 0x54(%0); \n\t" \ 107 "cache %1, 0x58(%0); cache %1, 0x5c(%0); \n\t" \ 108 "cache %1, 0x60(%0); cache %1, 0x64(%0); \n\t" \ 109 "cache %1, 0x68(%0); cache %1, 0x6c(%0); \n\t" \ 110 "cache %1, 0x70(%0); cache %1, 0x74(%0); \n\t" \ 111 "cache %1, 0x78(%0); cache %1, 0x7c(%0); \n\t" \ 112 ".set pop \n\t" \ 113 ".set reorder" \ 114 : \ 115 : "r" (va), "i" (op) \ 116 : "memory"); \ 117 } while (/*CONSTCOND*/0) 118 119 /* 120 * cache_tx39_op_32lines_16: 121 * 122 * Perform the specified cache operation on 32 16-byte 123 * cache lines. 124 */ 125 #define cache_tx39_op_32lines_16(va, op) \ 126 do { \ 127 __asm __volatile( \ 128 ".set noreorder \n\t" \ 129 ".set push \n\t" \ 130 ".set mips3 \n\t" \ 131 "cache %1, 0x000(%0); cache %1, 0x010(%0); \n\t" \ 132 "cache %1, 0x020(%0); cache %1, 0x030(%0); \n\t" \ 133 "cache %1, 0x040(%0); cache %1, 0x050(%0); \n\t" \ 134 "cache %1, 0x060(%0); cache %1, 0x070(%0); \n\t" \ 135 "cache %1, 0x080(%0); cache %1, 0x090(%0); \n\t" \ 136 "cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \n\t" \ 137 "cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \n\t" \ 138 "cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \n\t" \ 139 "cache %1, 0x100(%0); cache %1, 0x110(%0); \n\t" \ 140 "cache %1, 0x120(%0); cache %1, 0x130(%0); \n\t" \ 141 "cache %1, 0x140(%0); cache %1, 0x150(%0); \n\t" \ 142 "cache %1, 0x160(%0); cache %1, 0x170(%0); \n\t" \ 143 "cache %1, 0x180(%0); cache %1, 0x190(%0); \n\t" \ 144 "cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \n\t" \ 145 "cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \n\t" \ 146 "cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \n\t" \ 147 ".set pop \n\t" \ 148 ".set reorder" \ 149 : \ 150 : "r" (va), "i" (op) \ 151 : "memory"); \ 152 } while (/*CONSTCOND*/0) 153 154 void tx3900_icache_sync_all_16(void); 155 void tx3900_icache_sync_range_16(vaddr_t, vsize_t); 156 157 void tx3900_pdcache_wbinv_all_4(void); 158 159 void tx3900_pdcache_inv_range_4(vaddr_t, vsize_t); 160 void tx3900_pdcache_wb_range_4(vaddr_t, vsize_t); 161 162 void tx3920_icache_sync_all_16wb(void); 163 void tx3920_icache_sync_range_16wt(vaddr_t, vsize_t); 164 void tx3920_icache_sync_range_16wb(vaddr_t, vsize_t); 165 166 void tx3920_pdcache_wbinv_all_16wt(void); 167 void tx3920_pdcache_wbinv_all_16wb(void); 168 void tx3920_pdcache_wbinv_range_16wb(vaddr_t, vsize_t); 169 170 void tx3920_pdcache_inv_range_16(vaddr_t, vsize_t); 171 void tx3920_pdcache_wb_range_16wt(vaddr_t, vsize_t); 172 void tx3920_pdcache_wb_range_16wb(vaddr_t, vsize_t); 173 174 void tx3900_icache_do_inv_index_16(vaddr_t, vsize_t); 175 void tx3920_icache_do_inv_16(vaddr_t, vsize_t); 176 177 #endif /* !_LOCORE */ 178 #endif /* _KERNEL */ 179
Indexes created Wed Sep 24 15:09:51 GMT 2025