| History log of /src/sys/arch/mips/include/mips_opcode.h |
| Revision | | Date | Author | Comments |
| 1.26 |
| 05-Apr-2021 |
simonb | Some QED instructions are included in MIPS32 and MIPS64 instruction sets.
Update a few comments.
|
| 1.25 |
| 05-Apr-2021 |
simonb | Tidy up NOP disassembly, handle "pause" as well.
|
| 1.24 |
| 17-Aug-2020 |
mrg | branches: 1.24.4;
add a "special3 offset" type of decode to ddb disasm so we see the
offsets properly decoded. add mips r6 "cache" insn.
avoid signed/unsigned compare and ufetch_32() for upcoming crash(8).
|
| 1.23 |
| 15-Aug-2020 |
simonb | Fix value for SCE/SWE instructions.
Problem noticed by mrg@.
|
| 1.22 |
| 26-Jul-2020 |
simonb | #define<tab>
Nuke trailing whitespace.
|
| 1.21 |
| 27-Jun-2015 |
matt | More instructions
|
| 1.20 |
| 04-Jun-2015 |
matt | Add a lot of missing mipsNNr2 instruction + cavium specific instructions.
|
| 1.19 |
| 01-Jun-2015 |
matt | Rework cavium support in preparation for MULTIPROCESSOR support
|
| 1.18 |
| 18-Aug-2011 |
matt | branches: 1.18.12; 1.18.30;
Change bcond/BCOND to regimm/REGIMM to better match the MIPS nomenclature.
|
| 1.17 |
| 17-Aug-2011 |
matt | emulate the special3 opcode LX (lwx, ldx, lhx, lbux) instructions.
|
| 1.16 |
| 15-Mar-2011 |
matt | Remove redundant lines.
|
| 1.15 |
| 20-Feb-2011 |
matt | Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
|
| 1.14 |
| 07-Jul-2010 |
chs | branches: 1.14.2; 1.14.4;
implement emulation of the "rdhwr" instruction for mips TLS.
|
| 1.13 |
| 06-Aug-2009 |
msaitoh | branches: 1.13.2; 1.13.4;
Add disassemble code for DMT, DMF, MTH and MFH.
|
| 1.12 |
| 11-Dec-2005 |
christos | branches: 1.12.78; 1.12.96;
merge ktrace-lwp.
|
| 1.11 |
| 15-Oct-2003 |
simonb | One defintion of OP_SYNC should be enough.
|
| 1.10 |
| 07-Aug-2003 |
agc | Move UCB-licensed code from 4-clause to 3-clause licence.
Patches provided by Joel Baker in PR 22364, verified by myself.
|
| 1.9 |
| 06-Jul-2002 |
gmcgarry | branches: 1.9.6;
Overhaul the emulation facility. We do this by:
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()
Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.
Tested on r3k with and without SOFTFLOAT enabled.
|
| 1.8 |
| 13-Aug-2001 |
soda | branches: 1.8.6; 1.8.14;
OP_BLTZAL was defined twice.
|
| 1.7 |
| 11-Jul-2000 |
jeffs | branches: 1.7.4;
Add support for 3 QED special2 opcodes.
|
| 1.6 |
| 17-Oct-1997 |
jonathan | branches: 1.6.18;
Add bi-endian support to mips locore, <mips/endian.h>, and mips_opcode.h.
Derived from a change request (PR port-mips/4277) from
Tsubai Masanari, (tsubai@iri.co.jp).
|
| 1.5 |
| 23-Mar-1996 |
jonathan | Merge in additions of missing MIPS-I opcodes, and r4000-in-32-bit mode
opcodes from the Pica port. Per Fogelstrom claims the latter are all
supposedly MIPS-II (r6000) instructions, rather than MIPS-III (R4000),
but we haven't checked to be sure. Are LL/SC really in MIPS-II?
CVS:: ----------------------------------------------------------------------
|
| 1.4 |
| 26-Oct-1994 |
cgd | new RCS ID format.
|
| 1.3 |
| 27-May-1994 |
glass | bsd 4.4-lite pmax port as ported to NetBSD
|
| 1.2 |
| 27-May-1994 |
glass | upgrade to bsd 4.4-lite code base. only mod is rcsids
|
| 1.1 |
| 12-Oct-1993 |
deraadt | branches: 1.1.1;
Initial revision
|
| 1.1.1.1 |
| 12-Oct-1993 |
deraadt | pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
|
| 1.6.18.1 |
| 20-Nov-2000 |
bouyer | Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
|
| 1.7.4.2 |
| 06-Sep-2002 |
jdolecek | sync kqueue branch with HEAD
|
| 1.7.4.1 |
| 25-Aug-2001 |
thorpej | Merge Aug 24 -current into the kqueue branch.
|
| 1.8.14.1 |
| 16-Jul-2002 |
gehenna | catch up with -current.
|
| 1.8.6.2 |
| 01-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.8.6.1 |
| 13-Aug-2001 |
nathanw | file mips_opcode.h was added on branch nathanw_sa on 2002-08-01 02:42:31 +0000
|
| 1.9.6.3 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.9.6.2 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.9.6.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.12.96.4 |
| 04-Aug-2012 |
matt | disasm special2 and special3 opcodes (and ehb and ssnop too).
|
| 1.12.96.3 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.12.96.2 |
| 29-Dec-2010 |
matt | Add OPC_PREF and OPC_RSVD073
|
| 1.12.96.1 |
| 15-May-2010 |
matt | Add kernel support for MIPS TLS. Use rdhwr rt, $29 as defined by the MIPS
TLS spec so that Linux MIPS binaries will work. Use sysarch(MIPS_TINFOSET, v)
to set the pointer.
|
| 1.12.78.2 |
| 11-Aug-2010 |
yamt | sync with head.
|
| 1.12.78.1 |
| 19-Aug-2009 |
yamt | sync with head.
|
| 1.13.4.2 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.13.4.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.13.2.1 |
| 17-Aug-2010 |
uebayasi | Sync with HEAD.
|
| 1.14.4.1 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.14.2.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.18.30.2 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.18.30.1 |
| 06-Jun-2015 |
skrll | Sync with HEAD
|
| 1.18.12.1 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.24.4.1 |
| 17-Apr-2021 |
thorpej | Sync with HEAD.
|
