Home | History | Annotate | Download | only in include
History log of /src/sys/arch/mips/include/pte.h
RevisionDateAuthorComments
 1.27  22-Aug-2020  skrll Remove pte_zero_p and simply check against 0.
 1.26  26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.25  24-Jun-2017  skrll Provide pte_set
 1.24  04-Sep-2016  skrll Fix pte_cached_p for MIPS_HAS_R4K_MMU
 1.23  11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.22  27-Jun-2015  matt Remove unused struct pt_entry_t union.
 1.21  11-Jun-2015  matt Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now. It won't
be long until we switch to the uvm/pmap one.
 1.20  20-Feb-2011  matt branches: 1.20.14; 1.20.32;
Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.19  28-Apr-2008  martin branches: 1.19.18; 1.19.22; 1.19.28; 1.19.30;
Remove clause 3 and 4 from TNF licenses
 1.18  17-Oct-2007  garbled branches: 1.18.16; 1.18.18; 1.18.20;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.17  17-Jul-2007  macallan branches: 1.17.10;
add definitions for non-cached pages
 1.16  16-Feb-2006  perry branches: 1.16.24; 1.16.32;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.
 1.15  24-Dec-2005  perry branches: 1.15.2; 1.15.4; 1.15.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.14  25-Nov-2005  simonb More KNF.
 1.13  14-Oct-2002  chs branches: 1.13.6; 1.13.22; 1.13.30;
eliminate PT_ENTRY_NULL in favor of plain old NULL.
 1.12  05-Mar-2002  simonb Add support for MIPS32 and MIPS64 architectures:
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 1.11  23-Mar-2001  simonb branches: 1.11.2; 1.11.8;
Delete unused uvtopte() macro.
 1.10  09-Jun-2000  soda branches: 1.10.4;
rename
vad_to_pfn() -> mips_paddr_to_tlbpfn()
pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 1.9  09-Jun-2000  soda make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
 1.8  28-May-1999  nisimura branches: 1.8.2; 1.8.10;
- Make this compilable with MIPS1 or MIPS3 only configuration.
 1.7  27-May-1999  nisimura - Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
 1.6  06-Jan-1999  nisimura branches: 1.6.4;
- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.5  21-Jun-1997  mhitch branches: 1.5.12;
Cast mips1-only and mips3-only pfn_to_vad() macros to match the mips1/mips3
merged inline function. Fixes inconsist printf format usage in trap.c.
 1.4  17-Jun-1997  mhitch Remove stray macro definition; didn't hurt for MIPS1 only, but wrong for
MIPS3.
 1.3  16-Jun-1997  jonathan Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
 1.2  15-Jun-1997  mhitch More merged MIPS1/MIPS3 support. The pte definitions still need work before
they can be support both MIPS1 and MIPS3.
 1.1  13-Oct-1996  jonathan Merge mips1 and mips3 pte/pmap code, pass 0;
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h

* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h

* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.

* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)

* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.

* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
 1.5.12.2  19-Nov-1998  nisimura - And one more line escaped.
 1.5.12.1  19-Nov-1998  nisimura - Forgot to commit many files for vm_offset_t purge last Monday.
 1.6.4.1  21-Jun-1999  thorpej Sync w/ -current.
 1.8.10.1  22-Jun-2000  minoura Sync w/ netbsd-1-5-base.
 1.8.2.2  27-Mar-2001  bouyer Sync with HEAD.
 1.8.2.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.10.4.1  09-Apr-2001  nathanw Catch up with -current.
 1.11.8.3  18-Oct-2002  nathanw Catch up to -current.
 1.11.8.2  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.11.8.1  23-Mar-2001  nathanw file pte.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000
 1.11.2.1  16-Mar-2002  jdolecek Catch up with -current.
 1.13.30.1  29-Nov-2005  yamt sync with head.
 1.13.22.2  03-Sep-2007  yamt sync with head.
 1.13.22.1  21-Jun-2006  yamt sync with head.
 1.13.6.1  11-Dec-2005  christos Sync with head.
 1.15.6.1  22-Apr-2006  simonb Sync with head.
 1.15.4.1  09-Sep-2006  rpaulo sync with head
 1.15.2.1  18-Feb-2006  yamt sync with head.
 1.16.32.1  03-Oct-2007  garbled Sync with HEAD
 1.16.24.1  20-Aug-2007  ad Sync with HEAD.
 1.17.10.1  06-Nov-2007  matt sync with HEAD
 1.18.20.1  16-May-2008  yamt sync with head.
 1.18.18.1  18-May-2008  yamt sync with head.
 1.18.16.1  02-Jun-2008  mjf Sync with HEAD.
 1.19.30.1  05-Mar-2011  bouyer Sync with HEAD
 1.19.28.1  06-Jun-2011  jruoho Sync with HEAD.
 1.19.22.1  05-Mar-2011  rmind sync with head
 1.19.18.5  04-Aug-2012  matt Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
 1.19.18.4  11-Mar-2010  matt Mark some inlines as __pure.
 1.19.18.3  23-Feb-2010  matt Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
 1.19.18.2  26-Jan-2010  matt Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
 1.19.18.1  30-Dec-2009  matt Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
 1.20.32.3  28-Aug-2017  skrll Sync with HEAD
 1.20.32.2  05-Oct-2016  skrll Sync with HEAD
 1.20.32.1  22-Sep-2015  skrll Sync with HEAD
 1.20.14.1  03-Dec-2017  jdolecek update from HEAD

RSS XML Feed