pte.h revision 1.17
1 /* $NetBSD: pte.h,v 1.17 2007/07/17 03:53:56 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright 1996 The Board of Trustees of The Leland Stanford 42 * Junior University. All Rights Reserved. 43 * 44 * Permission to use, copy, modify, and distribute this 45 * software and its documentation for any purpose and without 46 * fee is hereby granted, provided that the above copyright 47 * notice appear in all copies. Stanford University 48 * makes no representations about the suitability of this 49 * software for any purpose. It is provided "as is" without 50 * express or implied warranty. 51 */ 52 53 #ifndef __MIPS_PTE_H__ 54 #define __MIPS_PTE_H__ 55 56 #include <mips/mips1_pte.h> 57 #include <mips/mips3_pte.h> 58 59 #define PG_ASID 0x000000ff /* Address space ID */ 60 61 #ifndef _LOCORE 62 #include <mips/cpu.h> 63 64 typedef union pt_entry { 65 unsigned int pt_entry; /* for copying, etc. */ 66 struct mips1_pte pt_mips1_pte; /* for getting to bits by name */ 67 struct mips3_pte pt_mips3_pte; 68 } pt_entry_t; 69 70 /* 71 * Macros/inline functions to hide PTE format differences. 72 */ 73 74 #define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */ 75 76 77 int pmap_is_page_ro(pmap_t, vaddr_t, int); 78 79 80 /* MIPS1-only */ 81 #if defined(MIPS1) && !defined(MIPS3_PLUS) 82 #define mips_pg_v(entry) ((entry) & MIPS1_PG_V) 83 #define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED) 84 85 #define mips_pg_m_bit() (MIPS1_PG_D) 86 #define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */ 87 #define mips_pg_ro_bit() (MIPS1_PG_RO) 88 #define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */ 89 #define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE) 90 #define mips_pg_rwncpage_bit() (MIPS1_PG_RWNCPAGE) 91 #define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE) 92 #define mips_pg_cwncpage_bit() (MIPS1_PG_CWNCPAGE) 93 #define mips_pg_global_bit() (MIPS1_PG_G) 94 #define mips_pg_wired_bit() (MIPS1_PG_WIRED) 95 96 #define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte)) 97 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va)) 98 99 #define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x)) 100 #define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x)) 101 #endif /* mips1 */ 102 103 104 /* MIPS3 (or greater) only */ 105 #if !defined(MIPS1) && defined(MIPS3_PLUS) 106 #define mips_pg_v(entry) ((entry) & MIPS3_PG_V) 107 #define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED) 108 109 #define mips_pg_m_bit() (MIPS3_PG_D) 110 #define mips_pg_rw_bit() (MIPS3_PG_D) 111 #define mips_pg_ro_bit() (MIPS3_PG_RO) 112 #define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE) 113 #define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE) 114 #define mips_pg_rwncpage_bit() (MIPS3_PG_RWNCPAGE) 115 #define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE) 116 #define mips_pg_cwncpage_bit() (MIPS3_PG_CWNCPAGE) 117 #define mips_pg_global_bit() (MIPS3_PG_G) 118 #define mips_pg_wired_bit() (MIPS3_PG_WIRED) 119 120 #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) 121 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) 122 123 #define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x)) 124 #define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x)) 125 #endif /* mips3 */ 126 127 /* MIPS1 and MIPS3 (or greater) */ 128 #if defined(MIPS1) && defined(MIPS3_PLUS) 129 130 static __inline int 131 mips_pg_v(unsigned int entry), 132 mips_pg_wired(unsigned int entry), 133 PAGE_IS_RDONLY(unsigned int pte, vaddr_t va); 134 135 static __inline unsigned int 136 mips_pg_wired_bit(void), mips_pg_m_bit(void), 137 mips_pg_ro_bit(void), mips_pg_rw_bit(void), 138 mips_pg_ropage_bit(void), 139 mips_pg_cwpage_bit(void), 140 mips_pg_rwpage_bit(void), 141 mips_pg_global_bit(void); 142 static __inline paddr_t PTE_TO_PADDR(unsigned int pte); 143 144 static __inline paddr_t mips_tlbpfn_to_paddr(unsigned int pfn); 145 static __inline unsigned int mips_paddr_to_tlbpfn(paddr_t pa); 146 147 148 static __inline int 149 mips_pg_v(entry) 150 unsigned int entry; 151 { 152 if (MIPS_HAS_R4K_MMU) 153 return (entry & MIPS3_PG_V); 154 return (entry & MIPS1_PG_V); 155 } 156 157 static __inline int 158 mips_pg_wired(entry) 159 unsigned int entry; 160 { 161 if (MIPS_HAS_R4K_MMU) 162 return (entry & MIPS3_PG_WIRED); 163 return (entry & MIPS1_PG_WIRED); 164 } 165 166 static __inline unsigned int 167 mips_pg_m_bit(void) 168 { 169 if (MIPS_HAS_R4K_MMU) 170 return (MIPS3_PG_D); 171 return (MIPS1_PG_D); 172 } 173 174 static __inline unsigned int 175 mips_pg_ro_bit(void) 176 { 177 if (MIPS_HAS_R4K_MMU) 178 return (MIPS3_PG_RO); 179 return (MIPS1_PG_RO); 180 } 181 182 static __inline unsigned int 183 mips_pg_rw_bit(void) 184 { 185 if (MIPS_HAS_R4K_MMU) 186 return (MIPS3_PG_D); 187 return (MIPS1_PG_RW); 188 } 189 190 static __inline unsigned int 191 mips_pg_ropage_bit(void) 192 { 193 if (MIPS_HAS_R4K_MMU) 194 return (MIPS3_PG_ROPAGE); 195 return (MIPS1_PG_RO); 196 } 197 198 static __inline unsigned int 199 mips_pg_rwpage_bit(void) 200 { 201 if (MIPS_HAS_R4K_MMU) 202 return (MIPS3_PG_RWPAGE); 203 return (MIPS1_PG_RWPAGE); 204 } 205 206 static __inline unsigned int 207 mips_pg_cwpage_bit(void) 208 { 209 if (MIPS_HAS_R4K_MMU) 210 return (MIPS3_PG_CWPAGE); 211 return (MIPS1_PG_CWPAGE); 212 } 213 214 215 static __inline unsigned int 216 mips_pg_global_bit(void) 217 { 218 if (MIPS_HAS_R4K_MMU) 219 return (MIPS3_PG_G); 220 return (MIPS1_PG_G); 221 } 222 223 static __inline unsigned int 224 mips_pg_wired_bit(void) 225 { 226 if (MIPS_HAS_R4K_MMU) 227 return (MIPS3_PG_WIRED); 228 return (MIPS1_PG_WIRED); 229 } 230 231 static __inline paddr_t 232 PTE_TO_PADDR(pte) 233 unsigned int pte; 234 { 235 if (MIPS_HAS_R4K_MMU) 236 return (MIPS3_PTE_TO_PADDR(pte)); 237 return (MIPS1_PTE_TO_PADDR(pte)); 238 } 239 240 static __inline int 241 PAGE_IS_RDONLY(pte, va) 242 unsigned int pte; 243 vaddr_t va; 244 { 245 if (MIPS_HAS_R4K_MMU) 246 return (MIPS3_PAGE_IS_RDONLY(pte, va)); 247 return (MIPS1_PAGE_IS_RDONLY(pte, va)); 248 } 249 250 static __inline paddr_t 251 mips_tlbpfn_to_paddr(pfn) 252 unsigned int pfn; 253 { 254 if (MIPS_HAS_R4K_MMU) 255 return (mips3_tlbpfn_to_paddr(pfn)); 256 return (mips1_tlbpfn_to_paddr(pfn)); 257 } 258 259 static __inline unsigned int 260 mips_paddr_to_tlbpfn(pa) 261 paddr_t pa; 262 { 263 if (MIPS_HAS_R4K_MMU) 264 return (mips3_paddr_to_tlbpfn(pa)); 265 return (mips1_paddr_to_tlbpfn(pa)); 266 } 267 #endif 268 269 #endif /* ! _LOCORE */ 270 271 #if defined(_KERNEL) && !defined(_LOCORE) 272 /* 273 * Kernel virtual address to page table entry and visa versa. 274 */ 275 #define kvtopte(va) \ 276 (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 277 #define ptetokv(pte) \ 278 ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 279 280 extern pt_entry_t *Sysmap; /* kernel pte table */ 281 extern u_int Sysmapsize; /* number of pte's in Sysmap */ 282 #endif /* defined(_KERNEL) && !defined(_LOCORE) */ 283 #endif /* __MIPS_PTE_H__ */ 284
Indexes created Mon Sep 29 03:10:08 GMT 2025