| History log of /src/sys/arch/mips/rmi/rmixl_spl.S |
| Revision | | Date | Author | Comments |
| 1.7 |
| 01-Sep-2021 |
andvar | fix few typos in comments.
|
| 1.6 |
| 01-Dec-2020 |
skrll | Trailing whitespace
|
| 1.5 |
| 26-Jul-2020 |
simonb | branches: 1.5.2;
Use EIMR/EIRR regs definitions from <mips/cpuregs.h>
|
| 1.4 |
| 19-Jun-2015 |
matt | Don't include <machine/param.h>
|
| 1.3 |
| 14-Apr-2011 |
cliff | branches: 1.3.14; 1.3.32;
- remove most of the PARANOIA code
- add COP0_SYNC and JR_HB_RA following CP0 after all
writes to STATUS or EIMR that change interrupt control.
- all interrupt control now done w/ EIMR, except for
initial set of IE in STATUS.
|
| 1.2 |
| 20-Feb-2011 |
matt | branches: 1.2.2;
Merge forward from matt-nb5-mips64.
|
| 1.1 |
| 21-Mar-2010 |
cliff | branches: 1.1.2; 1.1.4; 1.1.6;
file rmixl_spl.S was initially added on branch matt-nb5-mips64.
|
| 1.1.6.1 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.1.4.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.1.2.6 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.1.2.5 |
| 20-Sep-2010 |
cliff | - .set noreorder up top to avoid instruction reordering
- adopt bugfix suggested by Manuel Boyer for mips/spl.S:
in _splraise and _splsw_splhigh, reload L_CPU in case we were
preempted prior to interrupts being blocked (thanks).
|
| 1.1.2.4 |
| 28-May-2010 |
cliff | rmixl_spl.S:
- where possible, stop using CP0 STATUS to disable all interrupts,zero EIMR instead. more efficient since less meddling with CP0.
assume STATUS[IE] is normally set.
- add rmixl_spl_init_cpu(), to initialize cp0 interrupt control for this cpu
rmixl_intr.c:
- rmixl_intr_init_cpu() calls rmixl_spl_init_cpu()
to set up CP0 interrupt controls for this cpu
|
| 1.1.2.3 |
| 21-May-2010 |
cliff | - turn off PARANOIA
- except for softintr irqs, ipl_eimr_map is no longer const;
all other irq bits are set/cleared at interrupt establish/disestablish
- add _splsw_splddb
- in _splsw_splintr, correct the return IPL_NONE case, and clarify some comments
|
| 1.1.2.2 |
| 14-Apr-2010 |
cliff | insert nop in delay slots
- at end of _splsw_splvm and
- inside _splsw_splint
|
| 1.1.2.1 |
| 21-Mar-2010 |
cliff | add splswitch variant using RMI chip-specific EIRR/EIMR interrupt extensions
|
| 1.2.2.3 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.2.2.2 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.2.2.1 |
| 20-Feb-2011 |
rmind | file rmixl_spl.S was added on branch rmind-uvmplock on 2011-03-05 20:51:11 +0000
|
| 1.3.32.1 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.3.14.1 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.5.2.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
