rmixl_spl.S revision 1.3.32.1
1 /* $NetBSD: rmixl_spl.S,v 1.3.32.1 2015/09/22 12:05:47 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt (at) 3am-software.com>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_cputype.h" /* which mips CPU levels do we support? */ 33 34 #include <sys/cdefs.h> 35 36 #include <mips/asm.h> 37 #include <mips/cpuregs.h> 38 39 RCSID("$NetBSD: rmixl_spl.S,v 1.3.32.1 2015/09/22 12:05:47 skrll Exp $"); 40 41 #include "assym.h" 42 43 #define MAP_SCALESHIFT 3 44 #define RMIXL_SOFT_INT_MASK_1 (MIPS_SOFT_INT_MASK_1 >> 8) 45 #define RMIXL_SOFT_INT_MASK (MIPS_SOFT_INT_MASK >> 8) 46 #define RMIXL_INT_MASK_5 (MIPS_INT_MASK_5 >> 8) 47 #define RMIXL_EIRR_PRESERVE (RMIXL_INT_MASK_5 | RMIXL_SOFT_INT_MASK) 48 #define RMIXL_INT_MASK_1 (MIPS_INT_MASK_1 >> 8) 49 #define RMIXL_INT_MASK_5 (MIPS_INT_MASK_5 >> 8) 50 #define RMIXL_COP_0_EIRR _(9), 6 51 #define RMIXL_COP_0_EIMR _(9), 7 52 53 .set noreorder 54 55 /* 56 * Array of mask of bits to set in the EIMR when we go to a 57 * given hardware interrupt priority level. 58 * The softint bits in [IPL_NONE] and [IPL_SOFTCLOCK] should stay constant 59 * Hard intr bits are managed by rmixl_vec_establish and rmixl_vec_disestablish. 60 */ 61 .data 62 .globl _C_LABEL(ipl_eimr_map) 63 .type _C_LABEL(ipl_eimr_map),@object 64 .p2align MAP_SCALESHIFT 65 _C_LABEL(ipl_eimr_map): 66 .dword RMIXL_SOFT_INT_MASK /* IPL_NONE */ 67 .dword RMIXL_SOFT_INT_MASK_1 /* IPL_SOFT{CLOCK,BIO} */ 68 .dword 0 /* IPL_SOFT{NET,SERIAL} */ 69 .dword 0 /* IPL_VM */ 70 .dword 0 /* IPL_SCHED */ 71 .dword 0 /* IPL_DDB */ 72 .dword 0 /* IPL_HIGH */ 73 74 .text 75 76 /* 77 * initialize cp0 interrupt control for this cpu 78 * - set STATUS[IE] 79 * - clear EIRR and EIMR 80 * on return, all interrupts are disabled by EIMR 81 * 82 * henceforth STATUS[IE] is expected to remain normally set 83 * but may be cleared and restored for temporary interrupt disablement 84 * 85 * call before the first call to spl0 on this cpu 86 */ 87 LEAF_NOPROFILE(rmixl_spl_init_cpu) 88 mfc0 t0, MIPS_COP_0_STATUS # get STATUS 89 ori t0, MIPS_SR_INT_IE # set IE 90 mtc0 zero, MIPS_COP_0_STATUS ## disable all ints in STATUS 91 COP0_SYNC 92 dmtc0 zero, RMIXL_COP_0_EIMR ## " " " " EIMR 93 COP0_SYNC 94 dmtc0 zero, RMIXL_COP_0_EIRR ## clear EIRR 95 COP0_SYNC 96 mtc0 t0, MIPS_COP_0_STATUS ## set STATUS | IE 97 JR_HB_RA 98 END(rmixl_spl_init_cpu) 99 100 /* 101 * RMIXL processor interrupt control 102 * 103 * Used as building blocks for spl(9) kernel interface. 104 */ 105 106 _splraise: 107 /* 108 * a0 = EIMR bits requested to be set for this IPL 109 * a1 = this IPL (IPL_*) 110 * Can only use a0-a3 and v0-v1 111 * old IPL is returned in v0 112 */ 113 dmfc0 a2, RMIXL_COP_0_EIMR # save EIMR 114 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 115 COP0_SYNC 116 PTR_L a3, L_CPU(MIPS_CURLWP) ## 117 INT_L v0, CPU_INFO_CPL(a3) ## get current IPL from cpu_info 118 sltu v1, a1, v0 ## newipl < curipl 119 bnez v1, 1f ## yes, don't change. 120 nop 121 INT_S a1, CPU_INFO_CPL(a3) ## save IPL in cpu_info 122 dmtc0 a0, RMIXL_COP_0_EIMR ## set new EIMR 123 JR_HB_RA 124 1: 125 dmtc0 a2, RMIXL_COP_0_EIMR ## restore saved EIMR 126 JR_HB_RA 127 128 STATIC_LEAF(_splsw_splx) 129 STATIC_XLEAF(_splsw_splx_noprof) # does not get mcount hooks 130 PTR_LA v1, _C_LABEL(ipl_eimr_map) # get address of table 131 sll a2, a0, MAP_SCALESHIFT # convert IPL to array offset 132 PTR_ADDU v1, a2 # add to table addr 133 REG_L v1, (v1) # load EIMR bits for this IPL 134 135 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 136 COP0_SYNC 137 PTR_L a3, L_CPU(MIPS_CURLWP) ## get cpu_info 138 INT_S a0, CPU_INFO_CPL(a3) ## save IPL in cpu_info 139 dmtc0 v1, RMIXL_COP_0_EIMR ## set new EIMR 140 JR_HB_RA 141 END(_splsw_splx) 142 143 STATIC_LEAF(_splsw_spl0) 144 REG_L v1, _C_LABEL(ipl_eimr_map) + 8*IPL_NONE 145 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 146 COP0_SYNC 147 PTR_L a3, L_CPU(MIPS_CURLWP) ## get cpu_info 148 #if IPL_NONE == 0 149 INT_S zero, CPU_INFO_CPL(a3) ## save IPL in cpu_info 150 #else 151 #error IPL_NONE != 0 152 #endif 153 dmtc0 v1, RMIXL_COP_0_EIMR ## set new EIMR 154 JR_HB_RA 155 END(_splsw_spl0) 156 157 STATIC_LEAF(_splsw_setsoftintr) 158 dsrl a0, 8 # convert CAUSE bit to EIRR bit 159 and a0, RMIXL_SOFT_INT_MASK # restrict to softint bits 160 dmfc0 v1, RMIXL_COP_0_EIMR # save EIMR register 161 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 162 COP0_SYNC 163 dmfc0 v0, RMIXL_COP_0_EIRR ## load EIRR 164 and v0, RMIXL_EIRR_PRESERVE ## preserve clock & softints 165 or v0, a0 ## set new softint bit 166 dmtc0 v0, RMIXL_COP_0_EIRR ## store EIRR 167 COP0_SYNC 168 dmtc0 v1, RMIXL_COP_0_EIMR ## restore EIMR 169 JR_HB_RA 170 END(_splsw_setsoftintr) 171 172 STATIC_LEAF(_splsw_clrsoftintr) 173 dsrl a0, 8 # convert CAUSE bit to EIRR bit 174 and a0, RMIXL_SOFT_INT_MASK # restrict to softint bits 175 xor a0, RMIXL_EIRR_PRESERVE # clear from preserve mask 176 dmfc0 v1, RMIXL_COP_0_EIMR # save EIMR register 177 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 178 COP0_SYNC 179 dmfc0 v0, RMIXL_COP_0_EIRR ## load EIRR 180 and v0, a0 ## apply preserve mask 181 dmtc0 v0, RMIXL_COP_0_EIRR ## store EIRR 182 COP0_SYNC 183 dmtc0 v1, RMIXL_COP_0_EIMR ## restore EIMR 184 JR_HB_RA 185 END(_splsw_clrsoftintr) 186 187 STATIC_LEAF(_splsw_splraise) 188 move a1, a0 189 PTR_LA v1, _C_LABEL(ipl_eimr_map) 190 sll a2, a0, MAP_SCALESHIFT 191 PTR_ADDU v1, a2 192 REG_L a0, (v1) 193 b _splraise 194 nop 195 END(_splsw_splraise) 196 197 STATIC_LEAF(_splsw_splhigh) 198 STATIC_XLEAF(_splsw_splhigh_noprof) 199 dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts 200 COP0_SYNC 201 PTR_L a3, L_CPU(MIPS_CURLWP) ## get cpu_info from curlwp 202 li a1, IPL_HIGH ## 203 INT_L v0, CPU_INFO_CPL(a3) ## old IPL for return value 204 INT_S a1, CPU_INFO_CPL(a3) ## save IPL in cpu_info 205 ## interrupts remain disabled! 206 j ra # return 207 nop 208 END(_splsw_splhigh) 209 210 STATIC_LEAF(_splsw_splddb) 211 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_DDB 212 li a1, IPL_DDB 213 b _splraise 214 nop 215 END(_splsw_splddb) 216 217 STATIC_LEAF(_splsw_splsched) 218 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_SCHED 219 li a1, IPL_SCHED 220 b _splraise 221 nop 222 END(_splsw_splsched) 223 224 STATIC_LEAF(_splsw_splvm) 225 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_VM 226 li a1, IPL_VM 227 b _splraise 228 nop 229 END(_splsw_splvm) 230 231 STATIC_LEAF(_splsw_splsoftserial) 232 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_SOFTSERIAL 233 li a1, IPL_SOFTSERIAL 234 b _splraise 235 nop 236 END(_splsw_splsoftserial) 237 238 STATIC_LEAF(_splsw_splsoftnet) 239 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_SOFTNET 240 li a1, IPL_SOFTNET 241 b _splraise 242 nop 243 END(_splsw_splsoftnet) 244 245 STATIC_LEAF(_splsw_splsoftbio) 246 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_SOFTBIO 247 li a1, IPL_SOFTBIO 248 b _splraise 249 nop 250 END(_splsw_splsoftbio) 251 252 STATIC_LEAF(_splsw_splsoftclock) 253 REG_L a0, _C_LABEL(ipl_eimr_map) + 8*IPL_SOFTCLOCK 254 li a1, IPL_SOFTCLOCK 255 b _splraise 256 nop 257 END(_splsw_splsoftclock) 258 259 STATIC_LEAF(_splsw_splintr) 260 dmfc0 ta1, RMIXL_COP_0_EIRR # get active interrupts 261 # restrict to hard int bits: 262 and v1, ta1, RMIXL_SOFT_INT_MASK # v1 = ta1 & ~RMIXL_SOFT_INT_MASK 263 xor v1, ta1 # " " 264 265 li v0, IPL_NONE 266 PTR_LA ta3, _C_LABEL(ipl_eimr_map) + 8*IPL_VM 267 REG_L ta2, -8(ta3) # load 'enabled' bits for IPL_SOFTSERIAL 268 and v1, ta2 # apply to pending bits 269 beq v1, zero, 4f # if nothing pending... 270 nop # ... return IPL_NONE 271 272 li v0, IPL_VM # ipl=IPL_VM 273 1: 274 REG_L ta2, (ta3) # load 'enabled' bits for ipl 275 and ta2, v1 # any match to pending intrs? 276 beq ta2, zero, 2f # no, return ipl 277 PTR_ADDI ta3, 1 << MAP_SCALESHIFT # point to next entry 278 addiu v0, 1 # ipl++ 279 move v1, ta2 # update highest pending 280 b 1b # loop 281 nop 282 283 2: 284 /* 285 * Emulate the CP0_SR 'IM' bits in 'pending' 286 * - if clock intr is requested, set MIPS_INT_MASK_5 287 * - if other HW intr is requested, set MIPS_INT_MASK_1 as summary bit 288 * the RMI evbmips_iointr function will sort through 289 * individial EIRR requests 290 */ 291 li t2, RMIXL_INT_MASK_5 # load RMIXL_INT_MASK_5 292 and t1, v1, t2 # save count/compare intr request value 293 nor t0, zero, t2 # invert the mask 294 and v1, t0 # v1 &= ~RMIXL_INT_MASK_5 295 beq v1, zero, 3f # no non-clock intrs? skip ahead 296 li v1, RMIXL_INT_MASK_1 # use INT_MASK_1 as 'summary' bit 297 # for non-clock hw intrs 298 3: 299 or v1, t1 # combine clock and non-clock-summary 300 sll v1, MIPS_INT_MASK_SHIFT # shift to emulate COP0_SR 'IM' bits 301 4: 302 INT_S v1, (a0) # set a (fake) new pending mask 303 j ra # and return highest ipl pending 304 nop 305 END(_splsw_splintr) 306 307 STATIC_LEAF(_splsw_splcheck) 308 #ifdef PARANOIA 309 PTR_L t0, L_CPU(MIPS_CURLWP) 310 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 311 312 dmfc0 t0, RMIXL_COP_0_EIMR # get current EIMR 313 314 PTR_LA t2, _C_LABEL(ipl_eimr_map) 315 sll t1, MAP_SCALESHIFT # shift cpl to array index 316 PTR_ADDU t2, t1 317 REG_L t3, (t2) # load value 318 1: bne t0, t3, 1b # loop forever if not equal 319 nop 320 #endif /* PARANOIA */ 321 j ra 322 nop 323 END(_splsw_splcheck) 324 325 .rdata 326 .globl _C_LABEL(rmixl_splsw) 327 _C_LABEL(rmixl_splsw): 328 PTR_WORD _C_LABEL(_splsw_splhigh) 329 PTR_WORD _C_LABEL(_splsw_splsched) 330 PTR_WORD _C_LABEL(_splsw_splvm) 331 PTR_WORD _C_LABEL(_splsw_splsoftserial) 332 PTR_WORD _C_LABEL(_splsw_splsoftnet) 333 PTR_WORD _C_LABEL(_splsw_splsoftbio) 334 PTR_WORD _C_LABEL(_splsw_splsoftclock) 335 PTR_WORD _C_LABEL(_splsw_splraise) 336 PTR_WORD _C_LABEL(_splsw_spl0) 337 PTR_WORD _C_LABEL(_splsw_splx) 338 PTR_WORD _C_LABEL(_splsw_splhigh_noprof) 339 PTR_WORD _C_LABEL(_splsw_splx_noprof) 340 PTR_WORD _C_LABEL(_splsw_setsoftintr) 341 PTR_WORD _C_LABEL(_splsw_clrsoftintr) 342 PTR_WORD _C_LABEL(_splsw_splintr) 343 PTR_WORD _C_LABEL(_splsw_splcheck) 344
Indexes created Tue Oct 21 19:09:51 GMT 2025