| History log of /src/sys/arch/riscv/starfive/files.starfive |
| Revision | | Date | Author | Comments |
| 1.12 |
| 06-Sep-2025 |
thorpej | Step towards modularizing the Flattened Device Tree code.
Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller. Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.
Add the necessary attributes to the device / attach declarations for
each provider and consumer.
There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain). Provide weak stubs for these routines to handle
situations where there is no provider.
No actual code changed; NFCI.
|
| 1.11 |
| 08-Feb-2025 |
skrll | risc-v: add a JH7110 TRNG driver
|
| 1.10 |
| 03-Jan-2025 |
skrll | risc-v: add a StarFive JH71[01]0 temperature sensor driver
|
| 1.9 |
| 01-Jan-2025 |
skrll | risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.
Testing as working with xhci and nvme on VisionFive2.
Uses legacy PCI interrupts currently. MSIs to be added later.
pcihost_fdt code is 99% the same as the Arm version and should be shared.
|
| 1.8 |
| 11-Nov-2024 |
skrll | risc-v: add a specific driver for the JH7110 STG system controller
|
| 1.7 |
| 11-Nov-2024 |
skrll | risc-v: add a JH7110 PCIe PHY driver
|
| 1.6 |
| 11-Nov-2024 |
skrll | risc-v: Add initial JH7110 pin controller driver
|
| 1.5 |
| 26-Oct-2024 |
skrll | risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
|
| 1.4 |
| 27-Jul-2024 |
skrll | risc-v: split the jh7100 clock controller driver
In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
|
| 1.3 |
| 07-Feb-2024 |
skrll | branches: 1.3.2;
risc-v: add a driver the JH7100 pin controller
|
| 1.2 |
| 18-Jan-2024 |
skrll | risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
|
| 1.1 |
| 16-Jan-2024 |
skrll | risc-v: add a StarTech JH7100 SoC clock driver
The JH7100 is seen in the Beagle-V board.
|
| 1.3.2.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
