Cross Reference: /src/sys/arch/arm/nvidia/tegra124

Lines Matching defs:tclk
978 	struct tegra_clk *tclk;
986 	tclk = tegra124_car_clock_find_by_id(clock_id);
987 	if (tclk)
988 		return TEGRA_CLK_BASE(tclk);
996 	struct tegra_clk *tclk;
998 	tclk = tegra124_car_clock_find(name);
999 	if (tclk == NULL)
1002 	atomic_inc_uint(&tclk->refcnt);
1004 	return TEGRA_CLK_BASE(tclk);
1010 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1012 	KASSERT(tclk->refcnt > 0);
1014 	atomic_dec_uint(&tclk->refcnt);
1019     struct tegra_clk *tclk)
1021 	struct tegra_pll_clk *tpll = &tclk->u.pll;
1028 	KASSERT(tclk->type == TEGRA_CLK_PLL);
1030 	tclk_parent = tegra124_car_clock_find(tclk->parent);
1051     struct tegra_clk *tclk, u_int rate)
1053 	struct tegra_pll_clk *tpll = &tclk->u.pll;
1059 	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1130     struct tegra_clk *tclk, struct tegra_clk *tclk_parent)
1132 	struct tegra_mux_clk *tmux = &tclk->u.mux;
1138 	KASSERT(tclk->type == TEGRA_CLK_MUX);
1186     struct tegra_clk *tclk)
1188 	struct tegra_mux_clk *tmux = &tclk->u.mux;
1192 	KASSERT(tclk->type == TEGRA_CLK_MUX);
1208     struct tegra_clk *tclk)
1210 	struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div;
1213 	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1233     struct tegra_clk *tclk)
1235 	struct tegra_div_clk *tdiv = &tclk->u.div;
1241 	KASSERT(tclk->type == TEGRA_CLK_DIV);
1243 	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1280     struct tegra_clk *tclk, u_int rate)
1282 	struct tegra_div_clk *tdiv = &tclk->u.div;
1289 	KASSERT(tclk->type == TEGRA_CLK_DIV);
1291 	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1363     struct tegra_clk *tclk, bool enable)
1365 	struct tegra_gate_clk *tgate = &tclk->u.gate;
1370 	KASSERT(tclk->type == TEGRA_CLK_GATE);
1403 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1406 	switch (tclk->type) {
1408 		return tclk->u.fixed.rate;
1410 		return tegra124_car_clock_get_rate_pll(priv, tclk);
1418 		return tegra124_car_clock_get_rate_fixed_div(priv, tclk);
1420 		return tegra124_car_clock_get_rate_div(priv, tclk);
1422 		panic("tegra124: unknown tclk type %d", tclk->type);
1429 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1434 	switch (tclk->type) {
1443 		    rate * tclk->u.fixed_div.div);
1447 		return tegra124_car_clock_set_rate_pll(priv, tclk, rate);
1449 		return tegra124_car_clock_set_rate_div(priv, tclk, rate);
1451 		panic("tegra124: unknown tclk type %d", tclk->type);
1458 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1461 	if (tclk->type != TEGRA_CLK_GATE) {
1468 	return tegra124_car_clock_enable_gate(priv, tclk, true);
1474 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1476 	if (tclk->type != TEGRA_CLK_GATE)
1479 	return tegra124_car_clock_enable_gate(priv, tclk, false);
1486 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1490 	if (tclk->type != TEGRA_CLK_MUX) {
1498 	return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent);
1504 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1507 	switch (tclk->type) {
1513 		if (tclk->parent) {
1514 			tclk_parent = tegra124_car_clock_find(tclk->parent);
1518 		tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk);
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