Lines Matching refs:_name
292 #define CLK_FIXED(_name, _rate) { \
293 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
298 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
310 #define CLK_MUX(_name, _reg, _bits, _p) { \
311 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
322 #define CLK_FIXED_DIV(_name, _parent, _div) { \
323 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \
333 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \
343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
344 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
356 #define CLK_GATE_L(_name, _parent, _bits) \
357 CLK_GATE(_name, _parent, \
361 #define CLK_GATE_H(_name, _parent, _bits) \
362 CLK_GATE(_name, _parent, \
366 #define CLK_GATE_U(_name, _parent, _bits) \
367 CLK_GATE(_name, _parent, \
371 #define CLK_GATE_V(_name, _parent, _bits) \
372 CLK_GATE(_name, _parent, \
376 #define CLK_GATE_W(_name, _parent, _bits) \
377 CLK_GATE(_name, _parent, \
381 #define CLK_GATE_X(_name, _parent, _bits) \
382 CLK_GATE(_name, _parent, \
386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \
387 CLK_GATE(_name, _parent, _reg, _reg, _bits)
Indexes created Wed Oct 15 07:09:58 GMT 2025