Lines Matching defs:pll
90 struct rk_cru_pll *pll = &clk->u.pll;
105 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
106 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
107 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
108 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
110 if ((pll->flags & RK_PLL_RK3288) != 0) {
122 } else if ((pll->flags & RK_PLL_RK3588) != 0) {
160 struct rk_cru_pll *pll = &clk->u.pll;
167 if (pll->rates == NULL || rate == 0 || !HAS_GRF(sc))
170 for (int i = 0; i < pll->nrates; i++)
171 if (pll->rates[i].rate == rate) {
172 pll_rate = &pll->rates[i];
178 if ((pll->flags & RK_PLL_RK3288) != 0) {
181 } else if ((pll->flags & RK_PLL_RK3588) != 0) {
185 if (__SHIFTOUT(CRU_READ(sc, pll->mode_reg), pll->mode_mask) ==
187 CRU_WRITE(sc, pll->mode_reg,
188 pll->mode_mask << 16 |
189 __SHIFTIN(PLL_MODE_SLOW, pll->mode_mask));
194 CRU_WRITE(sc, pll->con_base + PLL_CON1,
199 CRU_WRITE(sc, pll->con_base + PLL_CON0,
202 CRU_WRITE(sc, pll->con_base + PLL_CON1,
207 CRU_WRITE(sc, pll->con_base + PLL_CON2,
212 CRU_WRITE(sc, pll->con_base + PLL_CON1,
218 if (CRU_READ(sc, pll->con_base + PLL_CON6) &
219 pll->lock_mask) {
230 CRU_WRITE(sc, pll->mode_reg,
231 pll->mode_mask << 16 |
232 __SHIFTIN(PLL_MODE_NORM, pll->mode_mask));
235 CRU_WRITE(sc, pll->con_base + PLL_CON0,
240 CRU_WRITE(sc, pll->con_base + PLL_CON1,
246 val = CRU_READ(sc, pll->con_base + PLL_CON2);
249 CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
251 /* Set PLL work mode to normal */
252 const uint32_t write_mask = pll->mode_mask << 16;
253 const uint32_t write_val = pll->mode_mask;
254 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
259 sc->sc_grf_soc_status) & pll->lock_mask)
277 struct rk_cru_pll *pll = &clk->u.pll;
281 return pll->parents[0];
Indexes created Thu Oct 02 01:09:59 GMT 2025