Lines Matching refs:UL
38 #define AUPCI_CMEM_HC (1UL<<31) /* host config */
39 #define AUPCI_CMEM_E (1UL<<28) /* cmem enable */
43 #define AUPCI_CONFIG_ERD (1UL<<27) /* error direction */
44 #define AUPCI_CONFIG_ET (1UL<<26) /* error target */
45 #define AUPCI_CONFIG_EF (1UL<<25) /* fatal error */
46 #define AUPCI_CONFIG_EP (1UL<<24) /* parity error */
47 #define AUPCI_CONFIG_EM (1UL<<23) /* multiple errors */
48 #define AUPCI_CONfIG_BM (1UL<<22) /* bad master */
49 #define AUPCI_CONFIG_PD (1UL<<20) /* PCI disable */
50 #define AUPCI_CONFIG_BME (1UL<<19) /* byte mask enable */
51 #define AUPCI_CONFIG_DR (1UL<<18) /* drive mode */
52 #define AUPCI_CONFIG_NC (1UL<<16) /* non-coherent */
53 #define AUPCI_CONFIG_IE (1UL<<15) /* interrupt enable */
54 #define AUPCI_CONFIG_IP (1UL<<13) /* perr int enable */
55 #define AUPCI_CONFIG_IS (1UL<<12) /* serr int enable */
56 #define AUPCI_CONFIG_IMM (1UL<<11) /* master abort int */
57 #define AUPCI_CONFIG_ITM (1UL<<10) /* target abort int */
58 #define AUPCI_CONFIG_ITT (1UL<<9) /* target abort int */
59 #define AUPCI_CONFIG_IPB (1UL<<8) /* perr rec int */
62 #define AUPCI_CONFIG_SIC_ADDR (1UL<<6)
63 #define AUPCI_CONFIG_SIC_DATA (2UL<<6)
64 #define AUPCI_CONFIG_SIC_ALL (3UL<<6)
65 #define AUPCI_CONFIG_SIC_MASK (3UL<<6)
66 #define AUPCI_CONFIG_ST (1UL<<5) /* swap on target */
67 #define AUPCI_CONFIG_SM (1UL<<4) /* swap on master */
68 #define AUPCI_CONFIG_AEN (1UL<<3) /* enable arbiter */
69 #define AUPCI_CONFIG_R2H (1UL<<2) /* req 2 high pri */
70 #define AUPCI_CONFIG_R1H (1UL<<1) /* req 1 high pri */
71 #define AUPCI_CONFIG_CH (1UL<<0) /* cpu high pri */
87 #define AUPCI_PRCFG_AM (1UL<<9) /* abort mask */
88 #define AUPCI_PRCFG_DM (1UL<<8) /* done mask */
93 #define AUPCI_PRSTAT_AI (1UL<<9) /* posted read abort */
94 #define AUPCI_PRSTAT_DI (1UL<<8) /* posted read done */
95 #define AUPCI_PRSTAT_PEND (1UL<<0) /* posted read pend */
Indexes created Sun Oct 19 02:09:48 GMT 2025