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      1 /* $NetBSD: aupcireg.h,v 1.2 2006/02/16 01:55:17 gdamore Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2006 Itronix Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Garrett D'Amore for Itronix Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of Itronix Inc. may not be used to endorse
     18  *    or promote products derived from this software without specific
     19  *    prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
     22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
     25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     28  * ON ANY THEORY OF LIABILITY, WHETHER IN
     29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31  * POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #ifndef _MIPS_ALCHEMY_DEV_AUPCIREG_H
     35 #define	_MIPS_ALCHEMY_DEV_AUPCIREG_H
     36 
     37 #define	AUPCI_CMEM			0x0000
     38 #define	  AUPCI_CMEM_HC			(1UL<<31)	/* host config */
     39 #define   AUPCI_CMEM_E			(1UL<<28)	/* cmem enable */
     40 
     41 #define AUPCI_CONFIG			0x0004
     42 #define	  AUPCI_CONFIG_EADDRH_SHIFT	28		/* bits 32-35 */
     43 #define	  AUPCI_CONFIG_ERD		(1UL<<27)	/* error direction */
     44 #define	  AUPCI_CONFIG_ET		(1UL<<26)	/* error target */
     45 #define	  AUPCI_CONFIG_EF		(1UL<<25)	/* fatal error */
     46 #define	  AUPCI_CONFIG_EP		(1UL<<24)	/* parity error */
     47 #define	  AUPCI_CONFIG_EM		(1UL<<23)	/* multiple errors */
     48 #define	  AUPCI_CONfIG_BM		(1UL<<22)	/* bad master */
     49 #define	  AUPCI_CONFIG_PD		(1UL<<20)	/* PCI disable */
     50 #define	  AUPCI_CONFIG_BME		(1UL<<19)	/* byte mask enable */
     51 #define   AUPCI_CONFIG_DR		(1UL<<18)	/* drive mode */
     52 #define	  AUPCI_CONFIG_NC		(1UL<<16)	/* non-coherent */
     53 #define	  AUPCI_CONFIG_IE		(1UL<<15)	/* interrupt enable */
     54 #define	  AUPCI_CONFIG_IP		(1UL<<13)	/* perr int enable */
     55 #define	  AUPCI_CONFIG_IS		(1UL<<12)	/* serr int enable */
     56 #define	  AUPCI_CONFIG_IMM		(1UL<<11)	/* master abort int */
     57 #define	  AUPCI_CONFIG_ITM		(1UL<<10)	/* target abort int */
     58 #define	  AUPCI_CONFIG_ITT		(1UL<<9)	/* target abort int */
     59 #define	  AUPCI_CONFIG_IPB		(1UL<<8)	/* perr rec int */
     60 #define	  AUPCI_CONFIG_SIC_SHIFT	6
     61 #define	  AUPCI_CONFIG_SIC_NONE		0
     62 #define	  AUPCI_CONFIG_SIC_ADDR		(1UL<<6)
     63 #define	  AUPCI_CONFIG_SIC_DATA		(2UL<<6)
     64 #define	  AUPCI_CONFIG_SIC_ALL		(3UL<<6)
     65 #define	  AUPCI_CONFIG_SIC_MASK		(3UL<<6)
     66 #define   AUPCI_CONFIG_ST		(1UL<<5)	/* swap on target */
     67 #define	  AUPCI_CONFIG_SM		(1UL<<4)	/* swap on master */
     68 #define	  AUPCI_CONFIG_AEN		(1UL<<3)	/* enable arbiter */
     69 #define	  AUPCI_CONFIG_R2H		(1UL<<2)	/* req 2 high pri */
     70 #define	  AUPCI_CONFIG_R1H		(1UL<<1)	/* req 1 high pri */
     71 #define	  AUPCI_CONFIG_CH		(1UL<<0)	/* cpu high pri */
     72 
     73 #define	AUPCI_B2BMASK			0x0008
     74 #define	  AUPCI_B2BMASK_SHIFT		16
     75 #define AUPCI_B2BBASE0			0x000C
     76 #define   AUPCI_B2BASE0_SHIFT		16
     77 #define	AUPCI_B2BBASE1			0x0010
     78 #define   AUPCI_B2BASE1_SHIFT		16
     79 #define	AUPCI_MWMASK			0x0014
     80 #define	  AUPCI_MWMASK_SHIFT		16
     81 #define	AUPCI_MWBASE			0x0018
     82 #define	  AUPCI_MWBASE_SHIFT		16
     83 #define	AUPCI_ERRADDR			0x001C
     84 #define	AUPCI_SPECINTACK		0x0020
     85 #define	AUPCI_PRCFG			0x0024
     86 #define   AUPCI_PRCFG_BLM_SHIFT		3
     87 #define	  AUPCI_PRCFG_AM		(1UL<<9)	/* abort mask */
     88 #define	  AUPCI_PRCFG_DM		(1UL<<8)	/* done mask */
     89 #define	  AUPCI_PRCFG_BS_SHIFT		4
     90 #define	  AUPCI_PRCFG_ADDR_HIGH_SHIFT	0
     91 #define	AUPCI_PRADDR			0x0028
     92 #define	AUPCI_PRSTAT			0x002C
     93 #define   AUPCI_PRSTAT_AI		(1UL<<9)	/* posted read abort */
     94 #define	  AUPCI_PRSTAT_DI		(1UL<<8)	/* posted read done */
     95 #define	  AUPCI_PRSTAT_PEND		(1UL<<0)	/* posted read pend */
     96 
     97 #define	AUPCI_ID		0x0100
     98 #define	AUPCI_COMMAND_STATUS	0x0104
     99 #define	AUPCI_CLASS		0x0108
    100 #define	AUPCI_MBAR		0x0110
    101 
    102 #endif	/* _MIPS_ALCHEMY_DEV_AUPCIREG_H */
    103