Lines Matching defs:cpu
50 #include <sys/cpu.h>
220 struct cpu_softc *cpu;
226 cpu = &octeon_cpu_softc[cpunum];
228 cpu->cpu_ip2_sum0 = X(CIU_IP2_SUM0(cpunum));
229 cpu->cpu_ip3_sum0 = X(CIU_IP3_SUM0(cpunum));
230 cpu->cpu_ip4_sum0 = X(CIU_IP4_SUM0(cpunum));
232 cpu->cpu_int_sum1 = X(CIU_INT_SUM1);
234 cpu->cpu_ip2_en[0] = X(CIU_IP2_EN0(cpunum));
235 cpu->cpu_ip3_en[0] = X(CIU_IP3_EN0(cpunum));
236 cpu->cpu_ip4_en[0] = X(CIU_IP4_EN0(cpunum));
238 cpu->cpu_ip2_en[1] = X(CIU_IP2_EN1(cpunum));
239 cpu->cpu_ip3_en[1] = X(CIU_IP3_EN1(cpunum));
240 cpu->cpu_ip4_en[1] = X(CIU_IP4_EN1(cpunum));
242 cpu->cpu_wdog = X(CIU_WDOG(cpunum));
243 cpu->cpu_pp_poke = X(CIU_PP_POKE(cpunum));
246 cpu->cpu_mbox_set = X(CIU_MBOX_SET(cpunum));
247 cpu->cpu_mbox_clr = X(CIU_MBOX_CLR(cpunum));
259 struct cpu_softc *cpu = &octeon_cpu_softc[cpunum];
263 cpu->cpu_ci = ci;
264 ci->ci_softc = cpu;
280 cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
281 cpu->cpu_ip3_enable[0] |= __BIT(CIU_INT_MBOX_31_16);
290 cpu->cpu_ip2_enable[bank],
291 cpu->cpu_ip3_enable[bank],
292 cpu->cpu_ip4_enable[bank]);
297 mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
298 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
299 mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
303 mips3_sd(cpu->cpu_mbox_clr, __BITS(31,0));
309 evcnt_attach_dynamic(&cpu->cpu_intr_evs[i],
338 struct cpu_softc *cpu;
375 cpu = &octeon_cpu_softc[0];
376 cpu->cpu_ip2_enable[bank] |= irq_mask;
377 mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
382 cpu = &octeon_cpu_softc[0];
383 cpu->cpu_ip3_enable[bank] |= irq_mask;
384 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
387 cpu = &octeon_cpu_softc[cpunum];
388 if (cpu->cpu_ci == NULL)
390 cpu->cpu_ip3_enable[bank] |= irq_mask;
391 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
399 cpu = &octeon_cpu_softc[0];
400 cpu->cpu_ip4_enable[bank] |= irq_mask;
401 mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
404 cpu = &octeon_cpu_softc[cpunum];
405 if (cpu->cpu_ci == NULL)
407 cpu->cpu_ip4_enable[bank] |= irq_mask;
408 mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
423 struct cpu_softc *cpu;
438 cpu = &octeon_cpu_softc[0];
439 cpu->cpu_ip2_enable[bank] &= ~irq_mask;
440 mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
445 cpu = &octeon_cpu_softc[cpunum];
446 if (cpu->cpu_ci == NULL)
448 cpu->cpu_ip3_enable[bank] &= ~irq_mask;
449 mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
456 cpu = &octeon_cpu_softc[cpunum];
457 if (cpu->cpu_ci == NULL)
459 cpu->cpu_ip4_enable[bank] &= ~irq_mask;
460 mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
481 struct cpu_softc * const cpu = ci->ci_softc;
489 const uint64_t sum1 = mips3_ld(cpu->cpu_int_sum1);
492 hwpend[0] = mips3_ld(cpu->cpu_ip4_sum0)
493 & cpu->cpu_ip4_enable[0];
494 hwpend[1] = sum1 & cpu->cpu_ip4_enable[1];
496 hwpend[0] = mips3_ld(cpu->cpu_ip3_sum0)
497 & cpu->cpu_ip3_enable[0];
498 hwpend[1] = sum1 & cpu->cpu_ip3_enable[1];
500 hwpend[0] = mips3_ld(cpu->cpu_ip2_sum0)
501 & cpu->cpu_ip2_enable[0];
502 hwpend[1] = sum1 & cpu->cpu_ip2_enable[1];
514 cpu->cpu_intr_evs[irq].ev_count++;
541 struct cpu_softc * const cpu = ci->ci_softc;
548 ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
553 mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
560 softint_schedule(cpu->cpu_wdog_sih);
601 struct cpu_softc * const cpu = ci->ci_softc;
609 mips3_sd(cpu->cpu_mbox_set, ipi_mask);
Indexes created Tue Sep 30 17:09:57 GMT 2025