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History log of /src/sys/arch/mips/cavium/octeon_intr.c
RevisionDateAuthorComments
 1.27  09-Apr-2022  riastradh mips/cavium: Insert appropriate membars around IPIs.
 1.26  26-Mar-2022  riastradh mips/cavium: Simplify membars around interrupt establishment.

Previously I used xc_barrier to ensure the initialization of the
struct octeon_intrhand was witnessed on all CPUs before publishing
it, in order to avoid needing any barrier on the usage side to be
issued by the interrupt handler.

But there's no need to avoid atomic_load_consume at time of
interrupt: on MIPS it's the same as atomic_load_relaxed anyway, so
there's no additional memory barrier cost here.
 1.25  23-Mar-2022  riastradh mips/cavium: Fix membars around establishing interrupt handlers.
 1.24  18-Aug-2020  skrll Fix MULTIPROCESSOR build
 1.23  17-Aug-2020  jmcneill IPI_SHOOTDOWN needs to be IPL_SCHED. Spotted by nick.
 1.22  05-Aug-2020  simonb Apply some static to some symbols.
 1.21  05-Aug-2020  simonb Target all device interrupts to cpu0.

Patch from skrll@. Code is conditional, hopefully not needed long term.
 1.20  20-Jul-2020  jmcneill Simplify IPI handling even more for now and run everything at IPL_HIGH.
 1.19  20-Jul-2020  jmcneill Fix confusion between ipi bitmask and mbox register bit assignments.
 1.18  17-Jul-2020  jmcneill Remove 2 CPU limit in OCTEON interrupt controller driver.
 1.17  17-Jul-2020  jmcneill Simplify IPI handling and change IPLs of IPI_HALT, IPI_XCALL, and
IPI_GENERIC from IPL_SCHED to IPL_HIGH.
 1.16  17-Jul-2020  jmcneill Cleanup handling of multiple banks.
 1.15  16-Jul-2020  jmcneill Support 128 IRQs instead of 64. This is icky and needs to be cleaned up.
 1.14  23-Jun-2020  simonb Don't include "opt_octeon.h" any more.
 1.13  20-Jun-2020  riastradh Nix trailing whitespace.
 1.12  19-Jun-2020  simonb Simplify interrupt definition: remove mostly unused masks and just
configure everything using interrupt numbers.
 1.11  31-May-2020  simonb Rename all Cavium Octeon device driver functions, structs etc from
"octeon_foo" to "octfoo", except "octeon_eth" becomes "cnmac".
 1.10  30-Mar-2017  skrll branches: 1.10.12;
Indentation
 1.9  28-Nov-2016  mrg branches: 1.9.2;
fix non-DIAG builds.
 1.8  31-Oct-2016  skrll Fixup IPI interrupt delivery and splsched mask so that
sys/uvm/pmap/pmap_tlb.c

541 KASSERTMSG(ci->ci_cpl >= IPL_SCHED,
542 "%s: cpl (%d) < IPL_SCHED (%d)",
543 __func__, ci->ci_cpl, IPL_SCHED);

doesn't fire.
 1.7  20-Aug-2016  skrll Need to set ci_request_ipis otherwise they won't get delivered.

Correct the test for the IPL_HIGH ipis
 1.6  12-Jul-2016  skrll branches: 1.6.2;
#include "opt_multiprocessor.h" as this file has #ifdef MULTIPROCESSOR
 1.5  11-Jul-2016  matt Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.4  06-Jun-2015  matt Add wdog support
cleanup IPI and MP support
Add NMI support.
 1.3  01-Jun-2015  matt branches: 1.3.2;
Rework cavium support in preparation for MULTIPROCESSOR support
 1.2  19-May-2015  matt Add per irq evcnt's
 1.1  29-Apr-2015  hikaru Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.3.2.6  28-Aug-2017  skrll Sync with HEAD
 1.3.2.5  05-Dec-2016  skrll Sync with HEAD
 1.3.2.4  05-Oct-2016  skrll Sync with HEAD
 1.3.2.3  22-Sep-2015  skrll Sync with HEAD
 1.3.2.2  06-Jun-2015  skrll Sync with HEAD
 1.3.2.1  01-Jun-2015  skrll file octeon_intr.c was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000
 1.6.2.3  26-Apr-2017  pgoyette Sync with HEAD
 1.6.2.2  07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.6.2.1  04-Nov-2016  pgoyette Sync with HEAD
 1.9.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.10.12.2  03-Dec-2017  jdolecek update from HEAD
 1.10.12.1  30-Mar-2017  jdolecek file octeon_intr.c was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000

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