Lines Matching refs:_SB_MAKEMASK1
240 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
241 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
242 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
243 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
250 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
251 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
252 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
253 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
254 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
265 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
266 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
267 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
268 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
269 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
270 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
271 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
280 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
281 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
288 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
299 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
300 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
301 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
302 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
303 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
307 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
308 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
310 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
311 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
313 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
314 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
315 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
317 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
318 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
321 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
355 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
371 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
392 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
393 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
421 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
422 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
445 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
497 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
498 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
499 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
500 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
501 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
536 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
537 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
538 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
539 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
540 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
541 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
542 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
543 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
545 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
573 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
574 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
575 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
576 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
577 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
578 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
579 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
662 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
663 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
664 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
665 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
666 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
667 #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
668 #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)
Indexes created Wed Oct 22 13:09:56 GMT 2025