1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 #ifndef _SB1250_SCD_H 49 #define _SB1250_SCD_H 50 51 #include "sb1250_defs.h" 52 53 /* ********************************************************************* 54 * System control/debug registers 55 ********************************************************************* */ 56 57 /* 58 * System Revision Register (Table 4-1) 59 */ 60 61 #define M_SYS_RESERVED _SB_MAKEMASK(8,0) 62 63 #define S_SYS_REVISION _SB_MAKE64(8) 64 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 65 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 66 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 67 68 #define K_SYS_REVISION_BCM1250_PASS1 0x01 69 70 #define K_SYS_REVISION_BCM1250_PASS2 0x03 71 #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ 72 #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ 73 #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ 74 #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ 75 #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ 76 #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ 77 #define K_SYS_REVISION_BCM1250_A9 0x08 78 #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 79 80 #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 81 #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 82 #define K_SYS_REVISION_BCM1250_B1 0x10 83 #define K_SYS_REVISION_BCM1250_B2 0x11 84 85 #define K_SYS_REVISION_BCM1250_C0 0x20 86 #define K_SYS_REVISION_BCM1250_C1 0x21 87 #define K_SYS_REVISION_BCM1250_C2 0x22 88 #define K_SYS_REVISION_BCM1250_C3 0x23 89 90 #if SIBYTE_HDR_FEATURE_CHIP(1250) 91 /* XXX: discourage people from using these constants. */ 92 #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 93 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 94 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 95 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 96 #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 97 #endif /* 1250 */ 98 99 #define K_SYS_REVISION_BCM112x_A1 0x20 100 #define K_SYS_REVISION_BCM112x_A2 0x21 101 #define K_SYS_REVISION_BCM112x_A3 0x22 102 #define K_SYS_REVISION_BCM112x_A4 0x23 103 #define K_SYS_REVISION_BCM112x_B0 0x30 104 105 #define K_SYS_REVISION_BCM1480_S0 0x01 106 #define K_SYS_REVISION_BCM1480_A1 0x02 107 #define K_SYS_REVISION_BCM1480_A2 0x03 108 #define K_SYS_REVISION_BCM1480_A3 0x04 109 #define K_SYS_REVISION_BCM1480_B0 0x11 110 111 /*Cache size - 23:20 of revision register*/ 112 #define S_SYS_L2C_SIZE _SB_MAKE64(20) 113 #define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) 114 #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) 115 #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) 116 117 #define K_SYS_L2C_SIZE_1MB 0 118 #define K_SYS_L2C_SIZE_512KB 5 119 #define K_SYS_L2C_SIZE_256KB 2 120 #define K_SYS_L2C_SIZE_128KB 1 121 122 #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB 123 #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB 124 #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB 125 126 127 /* Number of CPU cores, bits 27:24 of revision register*/ 128 #define S_SYS_NUM_CPUS _SB_MAKE64(24) 129 #define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) 130 #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) 131 #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) 132 133 134 /* XXX: discourage people from using these constants. */ 135 #define S_SYS_PART _SB_MAKE64(16) 136 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 137 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 138 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 139 140 /* XXX: discourage people from using these constants. */ 141 #define K_SYS_PART_SB1250 0x1250 142 #define K_SYS_PART_BCM1120 0x1121 143 #define K_SYS_PART_BCM1125 0x1123 144 #define K_SYS_PART_BCM1125H 0x1124 145 #define K_SYS_PART_BCM1122 0x1113 146 147 148 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 149 #define S_SYS_SOC_TYPE _SB_MAKE64(16) 150 #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 151 #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 152 #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 153 154 #define K_SYS_SOC_TYPE_BCM1250 0x0 155 #define K_SYS_SOC_TYPE_BCM1120 0x1 156 #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 157 #define K_SYS_SOC_TYPE_BCM1125 0x3 158 #define K_SYS_SOC_TYPE_BCM1125H 0x4 159 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 160 #define K_SYS_SOC_TYPE_BCM1x80 0x6 161 #define K_SYS_SOC_TYPE_BCM1x55 0x7 162 163 /* 164 * Calculate correct SOC type given a copy of system revision register. 165 * 166 * (For the assembler version, sysrev and dest may be the same register. 167 * Also, it clobbers AT.) 168 */ 169 #ifdef __ASSEMBLER__ 170 #define SYS_SOC_TYPE(dest, sysrev) \ 171 .set push ; \ 172 .set reorder ; \ 173 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 174 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 175 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 176 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 177 b 992f ; \ 178 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 179 992: \ 180 .set pop 181 #else 182 #define SYS_SOC_TYPE(sysrev) \ 183 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 184 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 185 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 186 #endif 187 188 #define S_SYS_WID _SB_MAKE64(32) 189 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 190 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 191 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 192 193 /* 194 * System Manufacturing Register 195 * Register: SCD_SYSTEM_MANUF 196 */ 197 198 #if SIBYTE_HDR_FEATURE_1250_112x 199 /* Wafer ID: bits 31:0 */ 200 #define S_SYS_WAFERID1_200 _SB_MAKE64(0) 201 #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 202 #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 203 #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 204 205 #define S_SYS_BIN _SB_MAKE64(32) 206 #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 207 #define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) 208 #define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 209 210 /* Wafer ID: bits 39:36 */ 211 #define S_SYS_WAFERID2_200 _SB_MAKE64(36) 212 #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 213 #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 214 #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 215 216 /* Wafer ID: bits 39:0 */ 217 #define S_SYS_WAFERID_300 _SB_MAKE64(0) 218 #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 219 #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 220 #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 221 222 #define S_SYS_XPOS _SB_MAKE64(40) 223 #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 224 #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 225 #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 226 227 #define S_SYS_YPOS _SB_MAKE64(46) 228 #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 229 #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 230 #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 231 #endif 232 233 234 /* 235 * System Config Register (Table 4-2) 236 * Register: SCD_SYSTEM_CFG 237 */ 238 239 #if SIBYTE_HDR_FEATURE_1250_112x 240 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 241 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 242 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 243 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 244 245 #define S_SYS_PLL_DIV _SB_MAKE64(7) 246 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 247 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 248 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 249 250 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 251 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 252 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 253 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 254 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 255 256 #define S_SYS_BOOT_MODE _SB_MAKE64(17) 257 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 258 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 259 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 260 #define K_SYS_BOOT_MODE_ROM32 0 261 #define K_SYS_BOOT_MODE_ROM8 1 262 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 263 #define K_SYS_BOOT_MODE_SMBUS_BIG 3 264 265 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 266 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 267 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 268 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 269 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 270 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 271 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 272 273 #define S_SYS_CONFIG 26 274 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 275 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 276 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 277 278 /* The following bits are writeable by JTAG only. */ 279 280 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 281 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 282 283 #define S_SYS_CLKCOUNT 34 284 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 285 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 286 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 287 288 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 289 290 #define S_SYS_PLL_IREF 43 291 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 292 293 #define S_SYS_PLL_VCO 45 294 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 295 296 #define S_SYS_PLL_VREG 47 297 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 298 299 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 300 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 301 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 302 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 303 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 304 305 /* End of bits writable by JTAG only. */ 306 307 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 308 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 309 310 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 311 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 312 313 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 314 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 315 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 316 317 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 318 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 319 320 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 321 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 322 #endif /* 1250 PASS2 || 112x PASS1 */ 323 324 #endif 325 326 327 /* 328 * Mailbox Registers (Table 4-3) 329 * Registers: SCD_MBOX_CPU_x 330 */ 331 332 #define S_MBOX_INT_3 0 333 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 334 #define S_MBOX_INT_2 16 335 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 336 #define S_MBOX_INT_1 32 337 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 338 #define S_MBOX_INT_0 48 339 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 340 341 /* 342 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 343 * Registers: SCD_WDOG_INIT_CNT_x 344 */ 345 346 #define V_SCD_WDOG_FREQ 1000000 347 348 #define S_SCD_WDOG_INIT 0 349 #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 350 351 #define S_SCD_WDOG_CNT 0 352 #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 353 354 #define S_SCD_WDOG_ENABLE 0 355 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 356 357 #define S_SCD_WDOG_RESET_TYPE 2 358 #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) 359 #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) 360 #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) 361 362 #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 363 #define K_SCD_WDOG_RESET_SOFT 1 364 #define K_SCD_WDOG_RESET_CPU0 3 365 #define K_SCD_WDOG_RESET_CPU1 5 366 #define K_SCD_WDOG_RESET_BOTH_CPUS 7 367 368 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ 369 #if SIBYTE_HDR_FEATURE(1250, PASS3) 370 #define S_SCD_WDOG_HAS_RESET 8 371 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) 372 #endif 373 374 375 /* 376 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 377 */ 378 379 #define V_SCD_TIMER_FREQ 1000000 380 381 #define S_SCD_TIMER_INIT 0 382 #define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) 383 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 384 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 385 386 #define V_SCD_TIMER_WIDTH 23 387 #define S_SCD_TIMER_CNT 0 388 #define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 389 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 390 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 391 392 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 393 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 394 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 395 396 /* 397 * System Performance Counters 398 */ 399 400 #define S_SPC_CFG_SRC0 0 401 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 402 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 403 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 404 405 #define S_SPC_CFG_SRC1 8 406 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 407 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 408 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 409 410 #define S_SPC_CFG_SRC2 16 411 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 412 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 413 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 414 415 #define S_SPC_CFG_SRC3 24 416 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 417 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 418 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 419 420 #if SIBYTE_HDR_FEATURE_1250_112x 421 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 422 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 423 #endif 424 425 426 /* 427 * Bus Watcher 428 */ 429 430 #define S_SCD_BERR_TID 8 431 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 432 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 433 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 434 435 #define S_SCD_BERR_RID 18 436 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 437 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 438 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 439 440 #define S_SCD_BERR_DCODE 22 441 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 442 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 443 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 444 445 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 446 447 448 #define S_SCD_L2ECC_CORR_D 0 449 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 450 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 451 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 452 453 #define S_SCD_L2ECC_BAD_D 8 454 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 455 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 456 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 457 458 #define S_SCD_L2ECC_CORR_T 16 459 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 460 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 461 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 462 463 #define S_SCD_L2ECC_BAD_T 24 464 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 465 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 466 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 467 468 #define S_SCD_MEM_ECC_CORR 0 469 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 470 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 471 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 472 473 #define S_SCD_MEM_ECC_BAD 8 474 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 475 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 476 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 477 478 #define S_SCD_MEM_BUSERR 16 479 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 480 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 481 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 482 483 484 /* 485 * Address Trap Registers 486 */ 487 488 #if SIBYTE_HDR_FEATURE_1250_112x 489 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 490 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 491 492 #define S_ATRAP_CFG_CNT 0 493 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 494 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 495 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 496 497 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 498 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 499 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 500 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 501 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 502 503 #define S_ATRAP_CFG_AGENTID 8 504 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 505 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 506 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 507 508 #define K_BUS_AGENT_CPU0 0 509 #define K_BUS_AGENT_CPU1 1 510 #define K_BUS_AGENT_IOB0 2 511 #define K_BUS_AGENT_IOB1 3 512 #define K_BUS_AGENT_SCD 4 513 #define K_BUS_AGENT_L2C 6 514 #define K_BUS_AGENT_MC 7 515 516 #define S_ATRAP_CFG_CATTR 12 517 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 518 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 519 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 520 521 #define K_ATRAP_CFG_CATTR_IGNORE 0 522 #define K_ATRAP_CFG_CATTR_UNC 1 523 #define K_ATRAP_CFG_CATTR_CACHEABLE 2 524 #define K_ATRAP_CFG_CATTR_NONCOH 3 525 #define K_ATRAP_CFG_CATTR_COHERENT 4 526 #define K_ATRAP_CFG_CATTR_NOTUNC 5 527 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 528 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 529 530 #endif /* 1250/112x */ 531 532 /* 533 * Trace Buffer Config register 534 */ 535 536 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 537 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 538 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 539 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 540 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 541 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 542 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 543 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 544 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 545 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 546 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 547 548 /* 549 * This field is the same on the 1250/112x and 1480, just located in 550 * a slightly different place in the register. 551 */ 552 #if SIBYTE_HDR_FEATURE_1250_112x 553 #define S_SCD_TRACE_CFG_CUR_ADDR 10 554 #else 555 #if SIBYTE_HDR_FEATURE_CHIP(1480) 556 #define S_SCD_TRACE_CFG_CUR_ADDR 24 557 #endif /* 1480 */ 558 #endif /* 1250/112x */ 559 560 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 561 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 562 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 563 564 /* 565 * Trace Event registers 566 */ 567 568 #define S_SCD_TREVT_ADDR_MATCH 0 569 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 570 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 571 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 572 573 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 574 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 575 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 576 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 577 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 578 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 579 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 580 581 #define S_SCD_TREVT_REQID 12 582 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 583 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 584 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 585 586 #define S_SCD_TREVT_RESPID 16 587 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 588 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 589 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 590 591 #define S_SCD_TREVT_DATAID 20 592 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 593 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 594 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 595 596 #define S_SCD_TREVT_COUNT 24 597 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 598 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 599 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 600 601 /* 602 * Trace Sequence registers 603 */ 604 605 #define S_SCD_TRSEQ_EVENT4 0 606 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 607 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 608 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 609 610 #define S_SCD_TRSEQ_EVENT3 4 611 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 612 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 613 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 614 615 #define S_SCD_TRSEQ_EVENT2 8 616 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 617 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 618 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 619 620 #define S_SCD_TRSEQ_EVENT1 12 621 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 622 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 623 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 624 625 #define K_SCD_TRSEQ_E0 0 626 #define K_SCD_TRSEQ_E1 1 627 #define K_SCD_TRSEQ_E2 2 628 #define K_SCD_TRSEQ_E3 3 629 #define K_SCD_TRSEQ_E0_E1 4 630 #define K_SCD_TRSEQ_E1_E2 5 631 #define K_SCD_TRSEQ_E2_E3 6 632 #define K_SCD_TRSEQ_E0_E1_E2 7 633 #define K_SCD_TRSEQ_E0_E1_E2_E3 8 634 #define K_SCD_TRSEQ_E0E1 9 635 #define K_SCD_TRSEQ_E0E1E2 10 636 #define K_SCD_TRSEQ_E0E1E2E3 11 637 #define K_SCD_TRSEQ_E0E1_E2 12 638 #define K_SCD_TRSEQ_E0E1_E2E3 13 639 #define K_SCD_TRSEQ_E0E1_E2_E3 14 640 #define K_SCD_TRSEQ_IGNORED 15 641 642 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 643 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 644 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 645 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 646 647 #define S_SCD_TRSEQ_FUNCTION 16 648 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 649 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 650 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 651 652 #define K_SCD_TRSEQ_FUNC_NOP 0 653 #define K_SCD_TRSEQ_FUNC_START 1 654 #define K_SCD_TRSEQ_FUNC_STOP 2 655 #define K_SCD_TRSEQ_FUNC_FREEZE 3 656 657 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 658 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 659 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 660 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 661 662 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 663 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 664 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 665 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 666 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 667 #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) 668 #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) 669 670 #endif 671
Indexes created Fri Sep 26 20:09:58 GMT 2025