Lines Matching refs:SCN_REG
41 /* per-channel regs (channel B's at SCN_REG(8-11)) */
42 #define CH_MR SCN_REG(0) /* rw mode register */
43 #define CH_SR SCN_REG(1) /* ro status register */
44 #define CH_CSR SCN_REG(1) /* wo clock select reg */
45 #define CH_CR SCN_REG(2) /* wo command reg */
46 #define CH_DAT SCN_REG(3) /* rw data reg */
49 #define DU_IPCR SCN_REG(4) /* ro input port change reg */
50 #define DU_ACR SCN_REG(4) /* wo aux control reg */
51 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */
52 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */
53 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */
54 #define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */
55 /* SCN_REG(8-11) channel b (see above) */
56 /* SCN_REG(12): reserved */
57 #define DU_IP SCN_REG(13) /* ro input port */
58 #define DU_OPCR SCN_REG(13) /* wo output port cfg reg */
59 #define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */
60 #define DU_OPSET SCN_REG(14) /* wo output port set */
61 #define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */
62 #define DU_OPCLR SCN_REG(15) /* wo output port reset */
Indexes created Tue Oct 14 00:09:49 GMT 2025