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Lines Matching refs:channel

47  * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
50 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
51 #define PIIX_IDETIM_SET(x, bytes, channel) \
52 	((x) | ((unsigned int)(bytes) << (16 * (channel))))
53 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \
54 	((x) & ~((unsigned int)(bytes) << (16 * (channel))))
74 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
76 #define PIIX_SIDETIM_ISP_SET(x, channel) \
77 	(x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4)))
78 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4))
80 #define PIIX_SIDETIM_RTC_SET(x, channel) \
81 	(x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4)))
88 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive)))
92 #define PIIX_UDMATIM_SET(x, channel, drive) \
93 	(((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
101 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive)))
102 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive)))
104 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive)))
130 #define ICH5_SATA_PI_PRI_NATIVE	0x01 /* Put Pri IDE channel in native mode */
131 #define ICH5_SATA_PI_SEC_NATIVE	0x04 /* Put Sec IDE channel in native mode */