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    Searched defs:CBUS_REG (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/arm/amlogic/
meson_wdt.c 42 #define CBUS_REG(x) ((x) << 2)
44 #define WATCHDOG_TC_REG CBUS_REG(0)
49 #define WATCHDOG_RESET_REG CBUS_REG(1)
mesongxbb_clkc.c 43 #define CBUS_REG(x) ((x) << 2)
45 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
46 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
47 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
48 #define HHI_GCLK_OTHER CBUS_REG(0x54)
49 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
50 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
51 #define HHI_NAND_CLK_CNTL CBUS_REG(0x97)
52 #define HHI_SD_EMMC_CLK_CNTL CBUS_REG(0x99)
53 #define HHI_MPLL_CNTL CBUS_REG(0xa0
    [all...]
mesongx_wdt.c 42 #define CBUS_REG(x) ((x) << 2)
44 #define WATCHDOG_CNTL CBUS_REG(0)
50 #define WATCHDOG_CNTL1 CBUS_REG(1)
51 #define WATCHDOG_TCNT CBUS_REG(2)
52 #define WATCHDOG_RESET CBUS_REG(3)
meson8b_clkc.c 49 #define CBUS_REG(x) ((x) << 2)
51 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
52 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
53 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
54 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
55 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
56 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67)
60 #define HHI_MPLL_CNTL CBUS_REG(0xa0)
61 #define HHI_MPLL_CNTL2 CBUS_REG(0xa1)
62 #define HHI_MPLL_CNTL5 CBUS_REG(0xa4
    [all...]
meson_usbphy.c 42 #define CBUS_REG(x) ((x) << 2)
43 #define PREI_USB_PHY_CFG_REG CBUS_REG(0x00)
45 #define PREI_USB_PHY_CTRL_REG CBUS_REG(0x01)
51 #define PREI_USB_PHY_ADP_BC_REG CBUS_REG(0x03)
mesong12a_pinctrl.c 40 #define CBUS_REG(n) ((n) << 2)
161 .reg = CBUS_REG((_off) * 3 + 0), \
166 .reg = CBUS_REG((_off) * 3 + 1), \
171 .reg = CBUS_REG((_off) * 3 + 2), \
176 .reg = CBUS_REG(_off), \
181 .reg = CBUS_REG(_off), \
291 .reg = CBUS_REG(_off), \
296 .reg = CBUS_REG((_off) + 4), \
301 .reg = CBUS_REG((_off) + 1), \
306 .reg = CBUS_REG((_off) + 3),
    [all...]
meson8b_pinctrl.c 37 #define CBUS_REG(n) ((n) << 2)
38 #define REG0 CBUS_REG(0)
39 #define REG1 CBUS_REG(1)
40 #define REG2 CBUS_REG(2)
41 #define REG3 CBUS_REG(3)
42 #define REG4 CBUS_REG(4)
43 #define REG5 CBUS_REG(5)
44 #define REG6 CBUS_REG(6)
45 #define REG7 CBUS_REG(7)
46 #define REG8 CBUS_REG(8
    [all...]
mesongxbb_pinctrl.c 37 #define CBUS_REG(n) ((n) << 2)
38 #define REG0 CBUS_REG(0)
39 #define REG1 CBUS_REG(1)
40 #define REG2 CBUS_REG(2)
41 #define REG3 CBUS_REG(3)
42 #define REG4 CBUS_REG(4)
43 #define REG5 CBUS_REG(5)
44 #define REG6 CBUS_REG(6)
45 #define REG7 CBUS_REG(7)
46 #define REG8 CBUS_REG(8
    [all...]
mesongxl_pinctrl.c 37 #define CBUS_REG(n) ((n) << 2)
38 #define REG0 CBUS_REG(0)
39 #define REG1 CBUS_REG(1)
40 #define REG2 CBUS_REG(2)
41 #define REG3 CBUS_REG(3)
42 #define REG4 CBUS_REG(4)
43 #define REG5 CBUS_REG(5)
44 #define REG6 CBUS_REG(6)
45 #define REG7 CBUS_REG(7)
46 #define REG8 CBUS_REG(8
    [all...]
mesong12_clkc.c 42 #define CBUS_REG(x) ((x) << 2)
44 #define HHI_GP0_PLL_CNTL0 CBUS_REG(0x10)
45 #define HHI_GP0_PLL_CNTL1 CBUS_REG(0x11)
46 #define HHI_GP0_PLL_CNTL2 CBUS_REG(0x12)
47 #define HHI_GP0_PLL_CNTL3 CBUS_REG(0x13)
48 #define HHI_GP0_PLL_CNTL4 CBUS_REG(0x14)
49 #define HHI_GP0_PLL_CNTL5 CBUS_REG(0x15)
50 #define HHI_GP0_PLL_CNTL6 CBUS_REG(0x16)
51 #define HHI_GP1_PLL_CNTL0 CBUS_REG(0x18)
52 #define HHI_GP1_PLL_CNTL1 CBUS_REG(0x19
    [all...]

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