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    Searched defs:isr (Results 1 - 25 of 96) sorted by relevancy

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  /src/sys/arch/amiga/amiga/
isr.h 1 /* $NetBSD: isr.h,v 1.13 2009/05/19 18:39:26 phx Exp $ */
31 * @(#)isr.h 7.1 (Berkeley) 5/8/90
37 struct isr { struct
38 struct isr *isr_forw;
39 struct isr *isr_back;
49 void add_isr(struct isr *);
50 void remove_isr(struct isr *);
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210_interrupts.c 38 * an abstracted bitmask of the data found in the ISR.
39 * Note that reading the ISR clear pending interrupts.
47 uint32_t isr; local
49 isr = OS_REG_READ(ah, AR_ISR);
50 if (isr == 0xffffffff) {
62 *masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
64 if (isr & AR_FATAL_INT)
66 if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
68 if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
72 * On fatal errors collect ISR state for debugging
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_interrupts.c 41 * the interrupt line, and returns both the masked and unmasked mapped ISR
51 uint32_t isr; local
53 isr = OS_REG_READ(ah, AR_ISR_RAC);
54 if (isr == 0xffffffff) {
59 *masked = isr & HAL_INT_COMMON;
61 if (isr & AR_ISR_HIUERR)
63 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
65 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
72 if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
79 * On fatal errors collect ISR state for debugging
    [all...]
  /src/sys/arch/arm/xscale/
iopi2c.c 85 uint32_t isr; local
92 * the ISR while the transfer is in progress--at least on the
106 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR);
107 if (isr & (bit | IIC_ISR_BED))
112 if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD)))
114 else if (isr & (bit & ~IIC_ISR_ALD))
121 "iopiic_wait, (%08x) error %d: ISR = 0x%08x\n",
122 bit, error, isr);
126 * read-only. So simply write back our copy of the ISR to clear any
129 bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr);
    [all...]
i80321_pci.c 230 uint32_t isr; local
244 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
246 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
pxa2x0_i2c.c 431 uint32_t isr; local
436 isr = CSR_READ_4(sc, I2C_ISR);
437 if (isr & (bit | ISR_BED))
442 if (isr & (ISR_BED | (bit & ISR_ALD)))
444 else if (isr & (bit & ~ISR_ALD))
449 CSR_WRITE_4(sc, I2C_ISR, isr);
674 uint16_t isr; local
676 isr = bus_space_read_4(iot, ioh, I2C_ISR);
678 isr & (ISR_BED|ISR_SAD|ISR_IRF|ISR_ITE|ISR_ALD|ISR_SSD));
680 DPRINTF(("%s: Interrupt Status 0x%x\n", __func__, isr));
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_interrupts.c 39 * Some platforms trigger our ISR before applying power to
47 * the interrupt line, and returns both the masked and unmasked mapped ISR
57 uint32_t isr, isr0, isr1; local
61 isr = OS_REG_READ(ah, AR_ISR);
63 if (isr & AR_ISR_BCNMISC) {
77 isr = OS_REG_READ(ah, AR_ISR_RAC);
78 if (isr == 0xffffffff) {
83 *masked = isr & HAL_INT_COMMON;
85 if (isr & AR_ISR_HIUERR)
87 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5416/
ar5416_interrupts.c 36 uint32_t isr; local
38 * Some platforms trigger our ISR before applying power to
41 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
42 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
45 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
54 * the interrupt line, and returns both the masked and unmasked mapped ISR
66 uint32_t isr, isr0, isr1, sync_cause local
    [all...]
  /src/sys/arch/arm/at91/
at91twi.c 146 u_int sr, isr, imr; local
150 isr = sr & imr;
152 if (!isr) {
159 if (isr & TWI_SR_TXCOMP) {
183 if (isr & TWI_SR_TXRDY) {
188 if (isr & TWI_SR_RXRDY) {
194 if (isr & (TWI_SR_TXRDY | TWI_SR_RXRDY) && sc->sc_resid <= 0) {
at91emac.c 211 uint32_t imr, isr, ctl; local
221 isr = EMAC_READ(ETH_ISR) & imr;
227 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
228 isr, rsr, imr));
230 if (isr & ETH_ISR_RBNA) { // out of receive buffers
240 if (isr & ETH_ISR_ROVR) {
247 if (isr & ETH_ISR_RCOM) { // packet has been received!
at91pio.c 406 uint32_t isr; local
408 isr = (PIO_READ(sc, PIO_ISR) & PIO_READ(sc, PIO_IMR));
409 if (!isr)
413 bit = ffs(isr) - 1;
414 isr &= ~(1U << bit);
417 panic("%s: isr is zero (0x%X)", __FUNCTION__, isr);
424 } while (isr);
  /src/sys/arch/hp300/dev/
if_le.c 248 uint16_t isr; local
250 isr = lerdcsr(sc, LE_CSR0);
252 if ((isr & LE_C0_INTR) == 0)
255 if (isr & LE_C0_RINT)
258 if (isr & LE_C0_TINT)
  /src/sys/dev/ic/
am7990.c 368 uint16_t isr; local
370 isr = (*sc->sc_rdcsr)(sc, LE_CSR0) | sc->sc_saved_csr0;
374 printf("%s: am7990_intr entering with isr=%04x\n",
375 device_xname(sc->sc_dev), isr);
377 if ((isr & LE_C0_INTR) == 0)
385 isr &= ~LE_C0_INEA;
386 (*sc->sc_wrcsr)(sc, LE_CSR0, isr);
390 isr & (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR |
393 if (isr & LE_C0_ERR) {
394 if (isr & LE_C0_BABL)
    [all...]
am79900.c 399 uint16_t isr; local
401 isr = (*sc->sc_rdcsr)(sc, LE_CSR0) | sc->sc_saved_csr0;
405 printf("%s: am79900_intr entering with isr=%04x\n",
406 device_xname(sc->sc_dev), isr);
408 if ((isr & LE_C0_INTR) == 0)
412 isr & (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR |
414 if (isr & LE_C0_ERR) {
415 if (isr & LE_C0_BABL) {
422 if (isr & LE_C0_CERR) {
428 if (isr & LE_C0_MISS)
    [all...]
  /src/sys/dev/mvme/
vme_two_isr.c 159 /* Clear out the ISR handler array */
221 struct vme_two_handler *isr; local
230 isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET];
231 if (isr->isr_hand)
232 (void) (*isr->isr_hand) (isr->isr_arg);
  /src/sys/arch/alpha/alpha/
dec_kn300.c 189 uint64_t isr; member in struct:__anon881
245 printf(fmt1, "Interrupt Status Reg.", ptr->isr);
  /src/sys/arch/emips/stand/common/
enic.c 122 unsigned int isr, saf, hi, lo, fl; local
135 isr = regs->Control;
137 if (isr & EC_ERROR) {
138 printf("enic: internal error %x\n", isr);
143 //printf("isr %x ",isr);
145 if ((isr & (EC_DONE|EC_OF_EMPTY)) == EC_DONE) {
  /src/sys/arch/evbmips/loongson/
loongson_intr.c 143 uint32_t isr0, isr, imr; local
154 isr = isr0 & imr & LOONGSON_INTRMASK_LVL4;
156 REGVAL(BONITO_INTENCLR) = isr;
160 if ((isr & (1 << irq)) == 0)
171 REGVAL(BONITO_INTENSET) = isr;
yeeloong_machdep.c 296 /* read ISR by default. */
310 /* read ISR by default. */
430 uint32_t isr, imr, mask; local
435 isr = lemote_get_isa_isr() & imr;
436 if (isr == 0)
446 if ((isr & mask) == 0)
467 if ((isr ^= mask) == 0)
  /src/sys/arch/mips/atheros/
ar_intr.c 198 uint32_t isr; local
203 isr = misc_intstat_get();
206 misc_intstat_put(isr & ~mask);
208 isr &= mask;
209 while (isr != 0) {
211 int index = 31 - __builtin_clz(isr & -isr); /* ffs */
218 isr >>= index + 1;
  /src/sys/arch/algor/algor/
algor_p6032_intr.c 377 uint32_t isr; local
397 isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
406 if (isr & irqmap->intbit) {
  /src/sys/arch/arm/sunxi/
sun4i_spi.c 383 uint32_t isr; local
385 isr = SPIREG_READ(sc, SPI_INT_STA);
386 if (!isr)
389 if (ISSET(isr, SPI_INT_STA_RO)) {
392 if (ISSET(isr, SPI_INT_STA_TU)) {
398 if (ISSET(isr, SPI_INT_STA_TC)) {
410 SPIREG_WRITE(sc, SPI_INT_STA, isr);
sun6i_spi.c 110 uint32_t gcr, isr; local
144 isr = SPIREG_READ(sc, SPI_INT_STA);
145 SPIREG_WRITE(sc, SPI_INT_STA, isr);
271 uint32_t isr, tcr; local
284 isr = SPIREG_READ(sc, SPI_INT_STA);
285 SPIREG_WRITE(sc, SPI_INT_STA, isr);
372 uint32_t isr; local
374 isr = SPIREG_READ(sc, SPI_INT_STA);
375 SPIREG_WRITE(sc, SPI_INT_STA, isr);
377 if (ISSET(isr, SPI_ISR_RX_RDY))
    [all...]
  /src/sys/arch/emips/ebus/
icap_ebus.c 363 u_int32_t isr, saf = 0, hi, lo; local
365 isr = sc->sc_dp->Control;
367 DEBUG_PRINT(("i %x\n",isr), DEBUG_INTR);
371 if ((isr & (ICAPC_INTEN|ICAPC_DONE)) != (ICAPC_INTEN|ICAPC_DONE))
376 while ((isr & ICAPC_OF_EMPTY) == 0) {
378 if (isr & ICAPC_ERROR) {
379 printf("%s: internal error (%x)\n", device_xname(sc->sc_dev),isr);
406 isr = sc->sc_dp->Control;
  /src/sys/arch/evbmips/gdium/
gdium_intr.c 301 uint32_t isr; local
308 isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
314 if (isr & (1 << ih->ih_irq)) {

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