| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_nkmp.c | 43 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sunxi_ccu_nkmp_enable
49 if (!nkmp->enable)
52 val = CCU_READ(sc, nkmp->reg);
54 val |= nkmp->enable;
56 val &= ~nkmp->enable;
57 CCU_WRITE(sc, nkmp->reg, val);
59 if (enable && nkmp->lock) {
61 val = CCU_READ(sc, nkmp->reg);
62 if (val & nkmp->lock
77 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sunxi_ccu_nkmp_get_rate
140 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sunxi_ccu_nkmp_set_rate
219 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sunxi_ccu_nkmp_get_parent
[all...] |
| sun8i_a83t_ccu.c | 138 const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;
139 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sun8i_a83t_ccu_cpux_set_rate
155 val = CCU_READ(sc, nkmp->reg);
158 CCU_WRITE(sc, nkmp->reg, val);
161 while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
178 .u.nkmp.reg = PLL_C0CPUX_CTRL_REG,
179 .u.nkmp.parent = "hosc",
180 .u.nkmp.n = __BITS(15,8),
181 .u.nkmp.k = 0
[all...] |
| sun9i_a80_ccu.c | 140 const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;
141 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp; local in function:sun9i_a80_ccu_cpux_set_rate
157 val = CCU_READ(sc, nkmp->reg);
158 val &= ~nkmp->n;
159 val |= __SHIFTIN(n, nkmp->n);
160 CCU_WRITE(sc, nkmp->reg, val);
163 while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
180 .u.nkmp.reg = PLL_C0CPUX_CTRL_REG,
181 .u.nkmp.parent = "hosc"
[all...] |
| sunxi_ccu.h | 134 .u.nkmp.reg = (_reg), \
135 .u.nkmp.parent = (_parent), \
136 .u.nkmp.n = (_n), \
137 .u.nkmp.k = (_k), \
138 .u.nkmp.m = (_m), \
139 .u.nkmp.p = (_p), \
140 .u.nkmp.enable = (_enable), \
141 .u.nkmp.flags = (_flags), \
142 .u.nkmp.lock = (_lock), \
143 .u.nkmp.table = (_tbl),
452 struct sunxi_ccu_nkmp nkmp; member in union:sunxi_ccu_clk::__anonaec1cae4010a
[all...] |
