| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv730_dpm.c | 50 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; local in function:rv730_populate_sclk_value
80 spll_func_cntl |= SPLL_DIVEN;
82 spll_func_cntl &= ~SPLL_DIVEN;
83 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
84 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
85 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
86 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
114 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
242 u32 spll_func_cntl; local in function:rv730_populate_smc_acpi_state
291 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl
[all...] |
| radeon_rv740_dpm.c | 130 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; local in function:rv740_populate_sclk_value
152 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
153 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
154 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
182 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
327 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; local in function:rv740_populate_smc_acpi_state
373 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
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| radeon_cypress_dpm.c | 1349 u32 spll_func_cntl = local in function:cypress_populate_smc_acpi_state
1434 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
1454 cpu_to_be32(spll_func_cntl);
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| radeon_rv770_dpm.c | 494 u32 spll_func_cntl = local in function:rv770_populate_sclk_value
527 spll_func_cntl |= SPLL_DIVEN;
529 spll_func_cntl &= ~SPLL_DIVEN;
530 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
531 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
532 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
533 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
561 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
932 u32 spll_func_cntl = local in function:rv770_populate_smc_acpi_state
981 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN
[all...] |
| radeon_ni_dpm.c | 1806 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; local in function:ni_populate_smc_acpi_state
1918 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
2009 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; local in function:ni_calculate_sclk_params
2033 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
2034 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2035 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2063 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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| radeon_ci_dpm.c | 3001 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; local in function:ci_populate_smc_acpi_level
3028 spll_func_cntl &= ~SPLL_PWRON;
3029 spll_func_cntl |= SPLL_RESET;
3034 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
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| radeon_si_dpm.c | 4498 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local in function:si_populate_smc_acpi_state
4602 cpu_to_be32(spll_func_cntl);
4792 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local in function:si_calculate_sclk_params
4815 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4816 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4817 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4845 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_ci_smumgr.c | 305 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:ci_calculate_sclk_params
329 /* SPLL_FUNC_CNTL setup */
330 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
332 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1388 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:ci_populate_smc_acpi_level
1418 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1420 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl
[all...] |
| amdgpu_fiji_smumgr.c | 867 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:fiji_calculate_sclk_params
891 /* SPLL_FUNC_CNTL setup */
892 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
894 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1314 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:fiji_populate_smc_acpi_level
1350 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1352 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL
[all...] |
| amdgpu_iceland_smumgr.c | 805 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:iceland_calculate_sclk_params
829 /* SPLL_FUNC_CNTL setup*/
830 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
832 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1436 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:iceland_populate_smc_acpi_level
1466 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1468 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl
[all...] |
| amdgpu_tonga_smumgr.c | 548 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:tonga_calculate_sclk_params
572 /* SPLL_FUNC_CNTL setup*/
573 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
575 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1188 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; local in function:tonga_populate_smc_acpi_level
1215 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1217 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 4962 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local in function:si_populate_smc_acpi_state
5067 cpu_to_be32(spll_func_cntl);
5256 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; local in function:si_calculate_sclk_params
5279 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5280 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5281 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5309 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
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