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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/
nouveau_nvkm_subdev_bios_timing.c 31 #include <subdev/bios/timing.h>
38 u32 timing = 0; local
42 timing = nvbios_rd32(bios, bit_P.offset + 4);
45 timing = nvbios_rd32(bios, bit_P.offset + 8);
47 if (timing) {
48 *ver = nvbios_rd08(bios, timing + 0);
51 *hdr = nvbios_rd08(bios, timing + 1);
52 *cnt = nvbios_rd08(bios, timing + 2);
53 *len = nvbios_rd08(bios, timing + 3);
56 return timing;
78 u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); local
    [all...]
  /src/sys/dev/fdt/
panel_fdt.c 91 const struct display_timing * const timing = local
111 if (strcmp(buf, "panel-timing") != 0)
116 aprint_error(": failed to parse panel-timing\n");
121 aprint_error(": missing panel-timing\n");
148 aprint_normal(": %dx%d", timing->hactive, timing->vactive);
  /src/regress/sys/kern/allocfree/
allocfree.c 59 static int timing; variable
79 num = prop_dictionary_get(props, "timing");
81 timing = (int)prop_number_integer_value(num);
158 if (timing) {
177 if (timing) {
257 timer = (timing ? "cpu_counter" : "nanotime");
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 106 uint32_t vertical_total_min = stream->timing.v_total;
111 vertical_blank_in_pixels = stream->timing.h_total *
113 - stream->timing.v_addressable);
115 * 10000 / stream->timing.pix_clk_100hz;
168 cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
169 cfg->v_refresh /= stream->timing.h_total;
170 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
171 / stream->timing.v_total;
241 const struct dc_crtc_timing *timing = local
242 &context->streams[0]->timing;
    [all...]
  /src/sys/arch/arm/fdt/
plfb_fdt.c 256 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing)
263 panel_timing = of_find_firstchild_byname(panel, "panel-timing");
267 return display_timing_parse(panel_timing, timing);
274 struct display_timing timing; local
276 if (plfb_get_panel_timing(sc, &timing) != 0) {
278 timing.hactive = 800;
279 timing.hback_porch = 128;
280 timing.hfront_porch = 24;
281 timing.hsync_len = 72;
282 timing.vactive = 600
    [all...]
  /src/sys/kern/
kern_softint.c 806 u_int timing; local
833 timing = softint_timing;
842 if (timing) {
849 if (timing) {
  /src/external/gpl3/gdb.old/dist/sim/bfin/
dv-bfin_otp.c 48 bu32 timing; member in struct:bfin_otp
163 case mmr_offset(timing):
210 case mmr_offset(timing):
280 otp->timing = 0x00001485;
  /src/external/gpl3/gdb.old/dist/sim/common/
cgen-engine.h 411 const INSN_TIMING *timing;
408 const INSN_TIMING *timing; member in struct:idesc
sim-model.h 36 /* Function unit and instruction timing support.
123 /* Pointer to timing table for this model. */
124 const INSN_TIMING *timing; member in struct:model
125 #define MODEL_TIMING(m) ((m)->timing)
  /src/external/gpl3/gdb/dist/sim/bfin/
dv-bfin_otp.c 48 bu32 timing; member in struct:bfin_otp
163 case mmr_offset(timing):
210 case mmr_offset(timing):
280 otp->timing = 0x00001485;
  /src/external/gpl3/gdb/dist/sim/common/
cgen-engine.h 411 const INSN_TIMING *timing;
408 const INSN_TIMING *timing; member in struct:idesc
sim-model.h 36 /* Function unit and instruction timing support.
123 /* Pointer to timing table for this model. */
124 const INSN_TIMING *timing; member in struct:model
125 #define MODEL_TIMING(m) ((m)->timing)
  /src/sys/dev/pcmcia/
pcmcia_cis.c 1051 u_int power, timing, iospace, irq, memspace, misc; local
1152 timing = reg & PCMCIA_TPCE_FS_TIMING;
1183 if (timing) {
1184 /* skip over timing, don't save */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 540 cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
541 cfg->v_refresh /= stream->timing.h_total;
542 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
543 / stream->timing.v_total;
559 vertical_blank_in_pixels = stream->timing.h_total *
560 (stream->timing.v_total
561 - stream->timing.v_addressable);
564 * 10000 / stream->timing.pix_clk_100hz;
661 const struct dc_crtc_timing *timing = local
662 &context->streams[0]->timing;
    [all...]
  /src/sys/dev/pci/
tdvfb.c 102 struct tdvfb_dac_timing *timing);
104 struct tdvfb_dac_timing *timing);
580 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */
619 struct tdvfb_dac_timing *timing)
626 /* write the timing for gfx clock into "slot" 0 */
628 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m);
629 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n);
648 struct tdvfb_dac_timing *timing)
655 /* write the timing for gfx clock into "slot" A */
657 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m)
680 struct tdvfb_dac_timing timing; local
    [all...]
  /src/sys/dev/sdmmc/
sdmmc_mem.c 310 * Switch to SDR12 timing
769 int timing = -1; local
777 timing = SDMMC_TIMING_UHS_SDR50;
780 timing = SDMMC_TIMING_UHS_SDR104;
788 timing = SDMMC_TIMING_MMC_HS200;
795 DPRINTF(("%s: execute tuning for timing %d\n", SDMMCDEVNAME(sc),
796 timing));
798 return sdmmc_chip_execute_tuning(sc->sc_sct, sc->sc_sch, timing);
1058 "card failed to switch to timing mode %d, using %d\n",
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_mst_types.c 523 struct dc_crtc_timing *timing; member in struct:dsc_mst_fairness_params
552 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
558 params[i].timing,
559 &params[i].timing->dsc_cfg)) {
560 params[i].timing->flags.DSC = 1;
561 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
563 params[i].timing->flags.DSC = 0;
578 (int) kbps, param.timing, &dsc_config);
767 stream->timing.flags.DSC = 0
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_stream.h 136 struct dc_crtc_timing timing; member in struct:dc_stream_state
371 * Phy, Encoder, Timing Generator are programmed and enabled.
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
stream_encoder.h 92 struct dc_crtc_timing timing; member in struct:encoder_unblank_param
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_ramgf100.c 37 #include <subdev/bios/timing.h>
145 } rammap, ramcfg, timing; local
175 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
177 if (!timing.data || ver != 0x10 || timing.size < 0x19) {
178 nvkm_error(subdev, "invalid/missing timing entry\n");
182 timing.data = 0;
nouveau_nvkm_subdev_fb_ramnv50.c 39 #include <subdev/bios/timing.h>
78 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)
103 timing[6] = (0x2d + T(CL) - T(CWL) +
109 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |
114 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
115 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
119 timing[2] = (T(CWL) - 1) << 24 |
123 timing[3] = (unkt3b - 2 + T(CL)) << 24 |
127 timing[4] = (cur4 & 0xffff0000) |
130 timing[5] = T(RFC) << 24
238 u32 timing[9]; local
    [all...]
nouveau_nvkm_subdev_fb_ramgt215.c 39 #include <subdev/bios/timing.h>
353 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
379 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
380 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
384 timing[2] = (T(CWL) - 1) << 24 |
388 timing[3] = (cur3 & 0x00ff0000) |
392 timing[4] = T(20) << 24 |
396 timing[5] = T(RFC) << 24 |
400 timing[6] = (0x5a + T(CL)) << 16 |
403 timing[7] = (cur7 & 0xff000000)
513 u32 timing[9]; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 627 /* TODO check if timing_changed, disable stream if timing changed */
638 &pipe_ctx->stream->timing);
655 &stream->timing,
706 /* TODO enable stream if timing changed */
929 &pipe_ctx->stream->timing);
932 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
949 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
950 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top
2220 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/bios/
ramcfg.h 117 unsigned timing[11]; member in struct:nvbios_ramcfg
  /src/sys/arch/arm/sunxi/
sunxi_mmc.c 511 int error, timing = SUNXI_MMC_TIMING_400K; local
515 timing = SUNXI_MMC_TIMING_400K;
517 timing = SUNXI_MMC_TIMING_25M;
520 timing = sc->sc_mmc_width == 8 ?
524 timing = SUNXI_MMC_TIMING_50M;
541 delays = &sc->sc_config->delays[timing];
882 /* For 8bits ddr in old timing modes, and all ddr in new
883 * timing modes, the module clock has to be 2x the card clock.
996 sunxi_mmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)
998 switch (timing) {
    [all...]

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