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    Searched defs:tpll (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/arm/nvidia/
tegra124_car.c 1021 struct tegra_pll_clk *tpll = &tclk->u.pll; local in function:tegra124_car_clock_get_rate_pll
1036 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1037 divm = __SHIFTOUT(base, tpll->divm_mask);
1038 divn = __SHIFTOUT(base, tpll->divn_mask);
1039 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1040 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1042 divp = __SHIFTOUT(base, tpll->divp_mask);
1053 struct tegra_pll_clk *tpll = &tclk->u.pll; local in function:tegra124_car_clock_set_rate_pll
1066 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1093 base = bus_space_read_4(bst, bsh, tpll->base_reg)
    [all...]
tegra210_car.c 1143 struct tegra_pll_clk *tpll = &tclk->u.pll; local in function:tegra210_car_clock_get_rate_pll
1158 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1159 divm = __SHIFTOUT(base, tpll->divm_mask);
1160 divn = __SHIFTOUT(base, tpll->divn_mask);
1161 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1162 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1163 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) {
1166 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) {
1168 divm *= __SHIFTOUT(base, tpll->divp_mask);
1170 divp = __SHIFTOUT(base, tpll->divp_mask)
1181 struct tegra_pll_clk *tpll = &tclk->u.pll; local in function:tegra210_car_clock_set_rate_pll
    [all...]

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