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  /src/sys/arch/arm/arm/
cpufunc_asm_arm10.S 43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
cpufunc_asm_arm11x6.S 70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
135 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
153 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
156 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
185 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
188 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range *
    [all...]
cpufunc_asm_arm67.S 59 mcrne p15, 0, r0, c5, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
102 mcr p15, 0, r0, c5, c0, 0
cpufunc_asm_armv6.S 52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
71 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
126 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
139 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
cpufunc_asm_sa1.S 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
198 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
217 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
268 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
304 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
cpufunc_asm_armv4.S 53 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
cpufunc_asm_xscale.S 122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
188 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
192 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
206 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
216 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
323 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
372 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
422 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry *
    [all...]
cpufunc_asm_arm9.S 64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
194 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
209 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
cpufunc_asm_armv5_ec.S 64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
187 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
202 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
cpufunc_asm_arm11.S 93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
103 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
106 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
cpufunc_asm_armv5.S 79 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
185 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
200 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
cpufunc_asm.S 59 * c5 - Fault status
80 mrc p15, 0, r0, c5, c0, 0
armv6_start.S 754 mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
869 mcr p15, 0, r0, c7, c5, 6 /* BPIALL - Branch predictor invalidate all */
1026 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
1027 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
1028 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
1029 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
cpufunc_asm_armv7.S 130 mcr p15, 0, r0, c7, c5, 6 @ branch predictor invalidate
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
300 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
319 mcr p15, 0, r0, c7, c5, 0
360 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 cache
cpufunc_asm_sheeva.S 198 mcr p15, 0, r0, c7, c5, 1
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/volt/
gk20a.h 34 int c5; member in struct:cvb_coef
nouveau_nvkm_subdev_volt_gk20a.c 35 /* MHz, c0, c1, c2, c3, c4, c5 */
69 * ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale)
80 DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
  /src/sys/arch/shark/stand/ofwboot/
srt0.S 72 mcr p15, 0, r0, c7, c5, 0 /* flush I$ */
  /src/sys/arch/acorn32/stand/boot32/
start.S 85 mcr p15, 0, r0, c5, c0, 0 /* flush TLB for v3 and v4 */
96 /*1*/ mcrne p15, 0, r1, c7, c5, 0 /* write zero in ARMv4 MMU disable */
144 mcr p15, 0, r0, c5, c0, 0 /* flush TLB for v3 and v4 */
  /src/sys/arch/evbarm/stand/board/
s3c2410_vector.S 81 mcr p15, 0, r2, c7, c5, 0
s3c2800_vector.S 113 mcr p15, 0, r2, c7, c5, 0
  /src/sys/arch/evbarm/gemini/
gemini_start.S 199 mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire I cache */
209 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB all */
  /src/sys/arch/epoc32/epoc32/
epoc32_start.S 201 mcr p15, 0, r0, c5, c0, 0 /* Flash TLB */
  /src/sys/stand/efiboot/bootarm/
cache.S 150 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 cache
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
r8a7740.dtsi 675 pd_c5: c5 {

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