| /src/sys/lib/libkern/arch/ia64/ |
| divdi3.S | 76 // q0 = a * y0 in f10
77 (p6) fma.s1 f10=f6,f8,f0
88 // q1 = q0 + e0 * q0 in f10
89 (p6) fma.s1 f10=f9,f10,f10
101 (p6) fma.s1 f9=f11,f10,f10
112 // r2 = a - b * q2 in f10
113 (p6) fnma.s1 f10=f7,f9,f
[all...] |
| moddi3.S | 56 // floating-point registers used: f6, f7, f8, f9, f10, f11, f12
84 // q0 = a * y0 in f10
85 (p6) fma.s1 f10=f6,f8,f0
96 // q1 = q0 + e0 * q0 in f10
97 (p6) fma.s1 f10=f9,f10,f10
115 (p6) fma.s1 f9=f11,f10,f10
126 // r2 = a - b * q2 in f10
[all...] |
| udivdi3.S | 78 // q0 = a * y0 in f10
79 (p6) fma.s1 f10=f6,f8,f0
90 // q1 = q0 + e0 * q0 in f10
91 (p6) fma.s1 f10=f9,f10,f10
103 (p6) fma.s1 f9=f11,f10,f10
114 // r2 = a - b * q2 in f10
115 (p6) fnma.s1 f10=f7,f9,f
[all...] |
| umoddi3.S | 55 // floating-point registers used: f6, f7, f8, f9, f10, f11, f12
79 // q0 = a * y0 in f10
80 (p6) fma.s1 f10=f6,f8,f0
91 // q1 = q0 + e0 * q0 in f10
92 (p6) fma.s1 f10=f9,f10,f10
110 (p6) fma.s1 f9=f11,f10,f10
121 // r2 = a - b * q2 in f10
[all...] |
| modsi3.S | 57 // floating-point registers used: f6, f7, f8, f9, f10, f11
83 (p6) fma.s1 f10=f6,f8,f0
94 (p6) fma.s1 f10=f8,f10,f10
104 (p6) fma.s1 f8=f8,f10,f10
|
| umodsi3.S | 57 // floating-point registers used: f6, f7, f8, f9, f10, f11
83 (p6) fma.s1 f10=f6,f8,f0
93 (p6) fma.s1 f10=f8,f10,f10
104 (p6) fma.s1 f8=f8,f10,f10
|
| /src/sys/arch/sparc/sparc/ |
| sigcode_state.s | 117 std %f10, [%sp + CCFSZ + 48]; \
144 ldd [%sp + CCFSZ + 48], %f10; \
|
| /src/sys/arch/hp300/dev/ |
| gboxreg.h | 96 uint8_t f10[0x68b9-0x6803-1]; member in struct:gboxfb
|
| topcatreg.h | 78 uint8_t f10[0x40ac-0x40a8-1]; member in struct:tcboxfb
|
| dvboxreg.h | 87 uint8_t f10[0x40ef-0x40d7-1]; member in struct:dvboxfb
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/ |
| tsan_ppc_regs.h | 43 #define f10 10 macro
|
| /src/lib/libc/compat/arch/sparc/sys/ |
| compat___sigtramp1.S | 109 std %f10, [%sp + CCFSZ + 48]; \
136 ldd [%sp + CCFSZ + 48], %f10; \
|
| /src/sys/arch/powerpc/powerpc/ |
| fpu_subr.S | 48 lfd %f10,FPREG_F10(%r3)
89 stfd %f10,FPREG_F10(%r3)
|
| /src/sys/arch/sparc64/sparc64/ |
| sigcode32.s | 127 std %f10, [%sp + CCFSZ + 48]
158 ldd [%sp + CCFSZ + 48], %f10
|
| sunos_sigcode.s | 127 std %f10, [%sp + CCFSZ + 48]
159 ldd [%sp + CCFSZ + 48], %f10
|
| /src/tests/ipf/ |
| t_filter_exec.sh | 120 test_case f10 dotest text text
153 atf_add_test_case f10
|
| /src/sys/arch/hp300/stand/common/ |
| grf_gbreg.h | 112 u_char f10[0x68b9-0x6803-1]; member in struct:gboxfb
|
| grf_tcreg.h | 102 u_char f10[0x40ac-0x40a8-1]; member in struct:tcboxfb
|
| /src/tests/ipf/input/ |
| Makefile | 9 f10 \
|
| /src/sys/arch/ia64/stand/ia64/efi/ |
| start.S | 230 setf.sig f10=r29 // so we can multiply
232 xma.lu f10=f10,f9,f8 // f10=symtab + r_sym*syment
234 getf.sig r29=f10
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 143 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
154 FN(reg, f10), v10)
304 #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
315 FN(reg, f10), v10)
317 #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
329 FN(reg, f10), v10, \
335 #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
347 FN(reg, f10), v10, \
358 #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
370 FN(reg, f10), v10,
[all...] |
| /src/tests/ipf/expected/ |
| Makefile | 11 f10 \
|
| /src/common/lib/libc/arch/sparc64/string/ |
| memcpy.S | 801 faligndata %f8, %f10, %f42
802 faligndata %f10, %f12, %f44
875 ldd [%o0], %f10
894 faligndata %f8, %f10, %f40
895 faligndata %f10, %f12, %f42
971 ldd [%o0], %f10
989 faligndata %f8, %f10, %f38
990 faligndata %f10, %f12, %f40
1065 ldd [%o0], %f10
1083 faligndata %f8, %f10, %f3
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/inc/protocol/ia64/ |
| eficontext.h | 111 UINT64 f10[2];
member in struct:__anon904514ee0108
|
| /src/tests/ipf/regress/ |
| Makefile | 11 f10 \
|
