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  /src/sys/arch/hp300/stand/common/
itereg.h 49 #define FONTDATA 0xA /* Offset from font address to font glyphs. */
itevar.h 113 #define KBD_SHIFT 0xA /* key + SHIFT */
  /src/sys/dev/i2c/
mpl115areg.h 47 #define MPL115A_C12_MSB 0xA
  /src/sys/arch/amiga/dev/
acafhreg.h 58 #define ACAFH_FLASH_WRITE 0xA
  /src/sys/dev/ic/
msm6242breg.h 49 #define MSM6242B_1YEAR 0xA
ds1286reg.h 106 #define DS1286_YEAR 0xA /* Time of year: year in century (0-99) */
nec71071reg.h 49 #define NEC71071_MODE 0xA /* Mode control register */
tcic2reg.h 49 #define TCIC_R_EDC 0xA /* Error detect code, 16 bit */
299 #define TCIC_SYSCFG_SIRQ10 (0xA) /* use IRQ10 */
635 #define TCIC_SCF1_IRQ10 (0xA) /* use IRQ10 */
am9513reg.h 87 #define AM9513_CM_SOURCE_GATE5 (0xA << 8)
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/net/
ti-dp83867.h 32 #define DP83867_RGMIIDCTL_2_75_NS 0xa
50 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
rv_ppsmc.h 44 #define PPSMC_MSG_PowerUpIspByTile 0xA
arcturus_ppsmc.h 49 #define PPSMC_MSG_DisableSmuFeaturesLow 0xA
smu_v11_0_ppsmc.h 47 #define PPSMC_MSG_DisableSmuFeaturesLow 0xA
smu_v12_0_ppsmc.h 45 #define PPSMC_MSG_PowerUpIspByTile 0xA
vega10_ppsmc.h 52 #define PPSMC_MSG_SetDriverDramAddrLow 0xA
vega12_ppsmc.h 49 #define PPSMC_MSG_DisableSmuFeaturesLow 0xA
vega20_ppsmc.h 48 #define PPSMC_MSG_DisableSmuFeaturesLow 0xA
  /src/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/dcn/
irqsrcs_dcn_1_0.h 194 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level
197 #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
200 #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
203 #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
206 #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
209 #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
212 #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
215 #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
218 #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
  /src/sys/dev/dec/
dzreg.h 121 #define DZ_LPR_B2400 0xA
  /src/sys/dev/pci/ixgbe/
ixgbe_dcb_82599.h 98 #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
  /src/sys/dev/qbus/
dhureg.h 117 #define DHU_LPR_B2400 0xA
  /src/sys/arch/macppc/dev/
dbdma.h 78 #define DBDMA_SCSI1 0xA
  /src/sys/dev/scsipi/
scsi_ctron_ether.h 24 #define CTRON_ETHER_SET_ADDR CTRON_ETHERCMD2(0xd, 0xA)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr_vbios_smu.c 55 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA
  /src/sys/dev/acpi/
acpi_cpu.h 40 #define ACPICPU_PDC_SMP 0xA
91 #define ACPICPU_T_STATE_RETRY 0xA

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