| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| iris_perf.h | 29 void iris_perf_init_vtbl(struct intel_perf_config *cfg);
|
| /xsrc/external/mit/fontconfig/dist/test/ |
| test-bz1744377.c | 39 FcConfig *cfg = FcConfigCreate (); local
41 if (!FcConfigParseAndLoadFromMemory (cfg, doc, FcTrue))
43 if (FcConfigParseAndLoadFromMemory (cfg, doc2, FcTrue))
45 if (!FcConfigParseAndLoadFromMemory (cfg, doc2, FcFalse))
48 FcConfigDestroy (cfg);
|
| test-issue180.c | 41 FcConfig *cfg = FcConfigCreate (); local
45 if (!FcConfigParseAndLoadFromMemory (cfg, doc, FcTrue))
50 l = FcConfigGetCacheDirs (cfg);
57 FcConfigDestroy (cfg);
59 cfg = FcConfigCreate ();
60 if (!FcConfigParseAndLoadFromMemory (cfg, doc2, FcTrue))
65 l = FcConfigGetCacheDirs (cfg);
72 FcConfigDestroy (cfg);
|
| /xsrc/external/mit/MesaLib/dist/src/panfrost/lib/ |
| pan_encoder.h | 100 pan_pack(attr, ATTRIBUTE_VERTEX_ID, cfg) {
102 cfg.divisor_r = __builtin_ctz(padded_count);
103 cfg.divisor_p = padded_count >> (cfg.divisor_r + 1);
106 cfg.divisor_r = 0x1F;
107 cfg.divisor_p = 0x4;
117 pan_pack(attr, ATTRIBUTE_INSTANCE_ID, cfg) {
120 cfg.divisor_p = ((1u << 31) - 1);
121 cfg.divisor_r = 0x1F;
122 cfg.divisor_e = 0x1
[all...] |
| pan_cs.c | 266 pan_pack(zs_crc_ext, ZS_CRC_EXTENSION, cfg) {
267 pan_prepare_crc(fb, rt_crc, &cfg);
268 cfg.zs_clean_pixel_write_enable = fb->zs.clear.z || fb->zs.clear.s;
269 pan_prepare_zs(fb, &cfg);
270 pan_prepare_s(fb, &cfg);
348 struct MALI_RENDER_TARGET *cfg)
364 cfg->srgb = true;
369 cfg->internal_format = fmt.internal;
370 cfg->writeback_format = fmt.writeback;
381 cfg->internal_format
[all...] |
| pan_blitter.c | 125 pan_pack(out, BLEND, cfg) {
127 cfg.enable = false;
129 cfg.internal.mode = MALI_BLEND_MODE_OFF;
134 cfg.round_to_fb_precision = true;
135 cfg.srgb = util_format_is_srgb(iview->format);
138 cfg.internal.mode = blend_shader ?
144 cfg.equation.rgb.a = MALI_BLEND_OPERAND_A_SRC;
145 cfg.equation.rgb.b = MALI_BLEND_OPERAND_B_SRC;
146 cfg.equation.rgb.c = MALI_BLEND_OPERAND_C_ZERO;
147 cfg.equation.alpha.a = MALI_BLEND_OPERAND_A_SRC
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/panfrost/vulkan/ |
| panvk_vX_cs.c | 147 pan_pack(attrib, ATTRIBUTE, cfg) {
149 cfg.buffer_index = varyings->varying[loc].buf;
150 cfg.offset = varyings->varying[loc].offset;
152 cfg.buffer_index =
156 cfg.offset_enable = PAN_ARCH == 5;
157 cfg.format = panvk_varying_hw_format(dev, varyings, stage, idx);
179 pan_pack(buf, ATTRIBUTE_BUFFER, cfg) {
183 cfg.type = 0;
184 cfg.special = special_id;
190 cfg.stride = varyings->buf[buf_idx].stride
[all...] |
| panvk_vX_meta.c | 41 pan_pack(vp.cpu, VIEWPORT, cfg) {
42 cfg.scissor_minimum_x = minx;
43 cfg.scissor_minimum_y = miny;
44 cfg.scissor_maximum_x = maxx;
45 cfg.scissor_maximum_y = maxy;
|
| panvk_vX_meta_clear.c | 166 pan_pack(rsd_ptr.cpu, RENDERER_STATE, cfg) {
167 pan_shader_prepare_rsd(shader_info, shader, &cfg);
168 cfg.properties.depth_source =
172 cfg.multisample_misc.depth_write_mask = z;
173 cfg.multisample_misc.sample_mask = UINT16_MAX;
174 cfg.multisample_misc.depth_function = MALI_FUNC_ALWAYS;
175 cfg.stencil_mask_misc.stencil_enable = s;
176 cfg.properties.stencil_from_shader = s;
177 cfg.stencil_mask_misc.stencil_mask_front = 0xFF;
178 cfg.stencil_mask_misc.stencil_mask_back = 0xFF
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| gfx7_l3_state.c | 71 setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
74 const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
75 const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
76 cfg->n[INTEL_L3P_ALL];
77 const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
78 cfg->n[INTEL_L3P_ALL];
79 const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] |
238 const struct intel_l3_config *const cfg = local
304 const struct intel_l3_config *const cfg = intel_get_default_l3_config(devinfo); local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| gen7_l3_state.c | 71 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
74 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
75 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
76 cfg->n[GEN_L3P_ALL];
77 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
78 cfg->n[GEN_L3P_ALL];
79 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] |
237 const struct gen_l3_config *const cfg = local
303 const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo); local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/intel/common/ |
| gen_l3_config.c | 201 gen_get_l3_config_weights(const struct gen_l3_config *cfg)
203 if (cfg) {
207 w.w[i] = cfg->n[i];
275 const struct gen_l3_config *const cfg = get_l3_configs(devinfo); local
276 assert(cfg == gen_get_l3_config(devinfo,
278 return cfg;
293 for (const struct gen_l3_config *cfg = cfgs; cfg->n[GEN_L3P_URB]; cfg++) {
294 const float dw = gen_diff_l3_weights(w0, gen_get_l3_config_weights(cfg));
[all...] |
| gen_l3_config.h | 80 gen_get_l3_config_weights(const struct gen_l3_config *cfg);
91 const struct gen_l3_config *cfg);
93 void gen_dump_l3_config(const struct gen_l3_config *cfg, FILE *fp);
|
| /xsrc/external/mit/xkbevd/dist/ |
| cfgparse.y | 118 CfgEntryPtr cfg;
119 cfg= calloc(1,sizeof(CfgEntryRec));
120 if (cfg) {
121 cfg->entry_type= VariableDef;
122 cfg->event_type= 0;
123 cfg->name.str= $1;
124 cfg->action.type= UnknownAction;
125 cfg->action.text= $3;
126 cfg->action.priv= 0;
127 cfg->next= NULL
[all...] |
| xkbevd.c | 81 "-cfg <file> Specify a config file\n"
104 else if (strcmp(argv[i], "-cfg") == 0) {
263 InterpretConfigs(CfgEntryPtr cfg)
265 config = cfg;
266 while (cfg != NULL) {
267 char *name = cfg->name.str;
268 if (cfg->entry_type == VariableDef) {
272 soundDir = cfg->action.text;
273 cfg->name.str = NULL;
274 cfg->action.text = NULL
370 CfgEntryPtr cfg, dflt; local
406 CfgEntryPtr cfg; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/asahi/ |
| agx_state.c | 190 agx_pack(out, RASTERIZER_FACE, cfg) {
191 cfg.depth_function = z_func;
192 cfg.disable_depth_write = disable_z_write;
195 cfg.stencil_write_mask = st.writemask;
196 cfg.stencil_read_mask = st.valuemask;
198 cfg.depth_pass = agx_stencil_ops[st.zpass_op];
199 cfg.depth_fail = agx_stencil_ops[st.zfail_op];
200 cfg.stencil_fail = agx_stencil_ops[st.fail_op];
202 cfg.stencil_compare = (enum agx_zs_func) st.func;
204 cfg.stencil_write_mask = 0xFF
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/glx/ |
| create_context.c | 42 struct glx_config *const cfg = (struct glx_config *) config; local
52 if (dpy == NULL || cfg == NULL)
59 psc = GetGLXScreenConfigs(dpy, cfg->screen);
63 assert(cfg->screen == psc->scr);
78 gc = psc->vtable->create_context_attribs(psc, cfg, share, num_attribs,
85 gc = applegl_create_context(psc, cfg, share, 0);
87 gc = indirect_create_context_attribs(psc, cfg, share, num_attribs,
107 cfg->fbconfigID,
108 cfg->screen,
|
| /xsrc/external/mit/MesaLib/dist/src/intel/ds/ |
| intel_pps_perf.cc | 36 , cfg {intel_perf_new(ralloc_cfg)}
44 intel_perf_init_metrics(cfg,
64 , cfg {o.cfg}
72 o.cfg = nullptr;
81 std::swap(cfg, o.cfg);
104 for (int i = 0; i < cfg->n_queries; ++i) {
105 struct intel_perf_query_info query = cfg->queries[i];
116 assert(cfg && "Intel perf config should be valid")
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/common/ |
| intel_l3_config.c | 213 intel_get_l3_config_weights(const struct intel_l3_config *cfg)
215 if (cfg) {
219 w.w[i] = cfg->n[i];
290 const struct intel_l3_config *const cfg = &list->configs[0]; local
291 assert(cfg == intel_get_l3_config(devinfo,
293 return cfg;
313 const struct intel_l3_config *cfg = &cfgs[i]; local
314 const float dw = intel_diff_l3_weights(w0, intel_get_l3_config_weights(cfg));
317 cfg_best = cfg;
352 const struct intel_l3_config *cfg)
[all...] |
| intel_l3_config.h | 80 intel_get_l3_config_weights(const struct intel_l3_config *cfg);
91 const struct intel_l3_config *cfg);
93 void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
|
| /xsrc/external/mit/xorg-server.old/dist/hw/dmx/ |
| dmx_glxvisuals.c | 518 __GLXvisualConfig *cfg = configs + (*nconfigs); local
548 memcpy(cfg, &glxConfigs[j], sizeof(__GLXvisualConfig) );
555 cfg->vid = fbcfg->associatedVisualId;
556 cfg->class = vinfo->class;
557 cfg->rgba = !(fbcfg->renderType & GLX_COLOR_INDEX_BIT_SGIX);
558 cfg->redSize = fbcfg->redBits;
559 cfg->greenSize = fbcfg->greenBits;
560 cfg->blueSize = fbcfg->blueBits;
561 cfg->alphaSize = fbcfg->alphaBits;
562 cfg->redMask = fbcfg->redMask
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/glx/ |
| create_context.c | 50 struct glx_config *const cfg = (struct glx_config *) config; local
72 if (cfg) {
73 screen = cfg->screen;
100 gc = psc->vtable->create_context_attribs(psc, cfg, share, num_attribs,
107 gc = applegl_create_context(psc, cfg, share, 0);
109 gc = indirect_create_context_attribs(psc, cfg, share, num_attribs,
129 cfg ? cfg->fbconfigID : 0,
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| brw_disasm_info.h | 45 /* Pointers to the basic block in the CFG if the instruction group starts
60 const struct cfg_t *cfg; member in struct:disasm_info
62 /** Block index in the cfg. */
72 const struct cfg_t *cfg);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/panfrost/ |
| pan_cmdstream.c | 188 pan_pack(&so->hw, SAMPLER, cfg) {
189 cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
190 cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
192 cfg.normalized_coordinates = cso->normalized_coords;
193 cfg.lod_bias = FIXED_16(cso->lod_bias, true);
194 cfg.minimum_lod = FIXED_16(cso->min_lod, false);
195 cfg.maximum_lod = FIXED_16(cso->max_lod, false);
197 cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s, using_nearest);
198 cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t, using_nearest);
199 cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r, using_nearest)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/ |
| etnaviv_query_acc_perfmon.c | 52 const struct etna_perfmon_config *cfg)
54 struct etna_perfmon_signal *signal = etna_pm_query_signal(perfmon, cfg->source);
105 const struct etna_perfmon_config *cfg; local
107 cfg = etna_pm_query_config(query_type);
108 if (!cfg)
111 if (!etna_pm_cfg_supported(ctx->screen->perfmon, cfg))
118 pm_add_signal(pq, ctx->screen->perfmon, cfg);
|
