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    Searched refs:restore (Results 1 - 25 of 93) sorted by relevancy

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  /xsrc/external/mit/xf86-video-siliconmotion/dist/src/
smilynx_hw.c 145 * This function performs the inverse of the restore function: It saves all the
320 * This function is used to restore a video mode. It writes out all of the
325 SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore)
338 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x17, restore->SR17);
339 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18, restore->SR18);
341 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x20, restore->SR20);
342 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, restore->SR21);
343 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, restore->SR22);
344 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23, restore->SR23);
345 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x24, restore->SR24)
    [all...]
smi_501.c 140 /* Also save accel state to properly restore kernel framebuffer */
366 SMI501_WriteMode(ScrnInfoPtr pScrn, MSOCRegPtr restore)
370 SMI501_WriteMode_common(pScrn, restore);
371 SMI501_WriteMode_lcd(pScrn, restore);
372 SMI501_WriteMode_crt(pScrn, restore);
374 SMI501_WriteMode_alpha(pScrn, restore);
378 WRITE_SCR(pSmi, ACCEL_SRC, restore->accel_src);
379 WRITE_SCR(pSmi, ACCEL_DST, restore->accel_dst);
380 WRITE_SCR(pSmi, ACCEL_DIM, restore->accel_dim);
381 WRITE_SCR(pSmi, ACCEL_CTL, restore->accel_ctl)
    [all...]
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_tv.c 349 /* Restore horizontal/vertical timing code tables */
351 RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore)
360 OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr);
361 hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
362 vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
365 tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]);
367 if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0)
372 tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore->v_code_timing[ i ])
1056 RADEONSavePtr restore = info->ModeReg; local
    [all...]
legacy_crtc.c 62 RADEONSavePtr restore)
71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl)
    [all...]
radeon_driver.c 323 * two channels with the two channels configured differently), restore
330 /* Restore the saved registers */
2317 * is enabled. Clear and restore FP2_ON around int10 to avoid this.
3756 /* restore the memory map here otherwise we may get a hang when
3790 * our local image to make sure we restore them properly on mode
3938 RADEONSavePtr restore)
3955 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc);
3958 (unsigned)restore->mc_agp_location);
3961 if (mc_fb_loc != restore->mc_fb_location ||
3962 mc_agp_loc != restore->mc_agp_location)
5829 RADEONSavePtr restore = info->SavedReg; local
    [all...]
legacy_output.c 247 RADEONSavePtr restore)
253 OUTREGP(RADEON_GPIOPAD_A, restore->gpiopad_a, ~1);
256 restore->dac_cntl,
260 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
264 OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
266 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
270 OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
272 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
275 OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl);
279 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl)
    [all...]
  /xsrc/external/mit/xterm/dist/vttests/
tab0.sh 79 restore() { function
118 restore
dynamic2.sh 108 eval restore=\$original"$N"
109 $CMD $OPT "$restore" >/dev/tty
  /xsrc/external/mit/xf86-video-s3/dist/src/
s3_Trio64DAC.c 112 S3RegPtr restore = &pS3->SavedRegs; local
115 outb(0x3c2, restore->dacregs[0]);
120 outb(0x3c5, restore->dacregs[2]);
122 outb(0x3c5, restore->dacregs[3]);
124 outb(0x3c5, restore->dacregs[4]);
126 outb(0x3c5, restore->dacregs[5]);
129 outb(0x3c5, restore->dacregs[8]);
131 outb(0x3c5, restore->dacregs[9]);
133 outb(0x3c5, restore->dacregs[10]);
135 outb(0x3c5, restore->dacregs[11])
    [all...]
s3_Ti.c 267 S3RegPtr restore = &pS3->SavedRegs; local
270 restore->dacregs[TIDAC_true_color_ctrl]);
272 restore->dacregs[TIDAC_multiplex_ctrl]);
274 restore->dacregs[TIDAC_clock_select]);
276 restore->dacregs[TIDAC_output_clock_select]);
278 restore->dacregs[TIDAC_general_ctrl]);
280 restore->dacregs[TIDAC_auxiliary_ctrl]);
283 restore->dacregs[TIDAC_general_io_data]);
286 restore->dacregs[TIDAC_pll_addr]);
288 restore->dacregs[0x40])
    [all...]
s3_GENDAC.c 117 for(i = 0; i < 2 * 3; i++) /* restore first two LUT entries */
338 S3RegPtr restore = &pS3->SavedRegs; local
345 outb(0x3c6, restore->dacregs[0]); /* Enhanced command register */
347 outb(0x3c9, restore->dacregs[3]); /* f2 PLL M divider */
348 outb(0x3c9, restore->dacregs[4]); /* f2 PLL N1/N2 divider */
350 outb(0x3c9, restore->dacregs[5]); /* PLL control */
351 outb(0x3c8, restore->dacregs[2]); /* PLL write index */
352 outb(0x3c7, restore->dacregs[1]); /* PLL read index */
  /xsrc/external/mit/xf86-video-r128/dist/src/
r128_crtc.c 253 void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
258 OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
260 OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
263 OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
264 OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
265 OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
266 OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
267 OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
268 OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
269 OUTREG(R128_CRTC_PITCH, restore->crtc_pitch)
    [all...]
r128_driver.c 2234 void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
2239 OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl | R128_FP_BLANK_DIS);
2241 OUTREG(R128_OVR_CLR, restore->ovr_clr);
2242 OUTREG(R128_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
2243 OUTREG(R128_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
2244 OUTREG(R128_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
2245 OUTREG(R128_MPP_TB_CONFIG, restore->mpp_tb_config );
2246 OUTREG(R128_MPP_GP_CONFIG, restore->mpp_gp_config );
2247 OUTREG(R128_SUBPIC_CNTL, restore->subpic_cntl);
2248 OUTREG(R128_VIPH_CONTROL, restore->viph_control)
2562 R128SavePtr restore = &info->SavedReg; local
    [all...]
r128.h 540 extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
541 extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
542 extern void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
543 extern void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
544 extern void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
545 extern void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
546 extern void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
547 extern void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
548 extern void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore);
549 extern void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore);
    [all...]
  /xsrc/external/mit/xf86-video-mga/dist/src/
mga_vga.c 20 MGAG200SERestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore)
112 /* restore the registers that were changed */
222 /* Restore clobbered registers */
246 MGAG200SERestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore)
253 if (restore->MiscOutReg & 0x01)
258 hwp->writeMiscOut(hwp, restore->MiscOutReg);
261 for (i = 1; i < restore->numSequencer; i++)
265 hwp->writeSeq(hwp, i, restore->Sequencer[i]);
278 hwp->writeCrtc(hwp, 17, restore->CRTC[17] & ~0x80);
280 for (i = 0; i < restore->numCRTC; i++
    [all...]
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i2c_vid.h 56 * Restore's the output's state at VT switch.
58 void (*restore)(I2CDevPtr d); member in struct:_I830I2CVidOutputRec
  /xsrc/external/mit/xf86-video-neomagic/dist/src/
neo_driver.c 133 NeoRegPtr restore);
2173 * routines will restore the proper values on server exit.
2176 neoProgramShadowRegs(ScrnInfoPtr pScrn, vgaRegPtr VgaReg, NeoRegPtr restore)
2204 if (restore->PanelDispCntlReg2 & 0x84) {
2225 if (restore->PanelDispCntlReg2 & 0x84) {
2419 neoRestore(ScrnInfoPtr pScrn, vgaRegPtr VgaReg, NeoRegPtr restore,
2433 neoProgramShadowRegs(pScrn, VgaReg, restore);
2437 VGAwGR(0x0A,restore->GeneralLockReg);
2451 temp |= (restore->ExtColorModeSelect & ~0xF0);
2462 temp |= (restore->ExtColorModeSelect & ~0x70)
    [all...]
  /xsrc/external/mit/ctwm/dist/
win_utils.h 17 int restore_mask(Window w, long restore);
  /xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/
vgaHW.h 197 vgaRegPtr restore);
198 extern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
200 vgaRegPtr restore);
201 extern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore,
  /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/vgahw/
vgaHW.h 202 extern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore);
203 extern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
204 extern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore);
205 extern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags);
vgaHW.c 729 vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore)
822 /* restore the registers that were changed */
843 vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore)
848 if (restore->MiscOutReg & 0x01)
853 hwp->writeMiscOut(hwp, restore->MiscOutReg);
855 for (i = 1; i < restore->numSequencer; i++)
856 hwp->writeSeq(hwp, i, restore->Sequencer[i]);
859 hwp->writeCrtc(hwp, 17, restore->CRTC[17] & ~0x80);
861 for (i = 0; i < restore->numCRTC; i++)
862 hwp->writeCrtc(hwp, i, restore->CRTC[i])
    [all...]
  /xsrc/external/mit/xf86-video-s3virge/dist/src/
s3v_driver.c 1395 * to restore the previous (text) mode.
1415 /* Restore standard register access */
1427 * This function performs the inverse of the restore function: It saves all
1740 * This function is used to restore a video mode. It writes out all
1751 S3VWriteMode (ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, S3VRegPtr restore)
1767 ps3v->STREAMSRunning = restore->CR67 & 0x0c;
1786 /* Restore S3 extended regs */
1788 VGAOUT8(vgaCRReg, restore->CR63);
1790 VGAOUT8(vgaCRReg, restore->CR66);
1792 VGAOUT8(vgaCRReg, restore->CR3A)
    [all...]
  /xsrc/external/mit/xf86-video-savage/dist/src/
savage_driver.c 1112 * standard vgaHWSave and Restore routines.
2465 SavageRegPtr restore, Bool Entering)
2477 TRACE(("SavageWriteMode(%x)\n", restore->mode));
2488 SavageSetVESAMode( psav, restore->mode | 0x8000, restore->refresh );
2503 if( psav->UseBIOS && restore->mode > 0x13 )
2510 SavageSetVESAMode( psav, restore->mode | 0x8000, restore->refresh );
2512 /* Restore the DAC. */
2544 VGAOUT8(vgaCRReg, restore->CR67)
    [all...]
  /xsrc/external/mit/xterm/dist/
resize.c 153 static const char *const restore[EMULATIONS] = variable
541 if (restore[emu])
542 IGNORE_RC(write(tty, restore[emu], strlen(restore[emu])));
  /xsrc/external/mit/xf86-video-nv/dist/src/
riva_dac.c 165 int restore = VGA_SR_MODE; local
167 restore |= primary ? (VGA_SR_CMAP | VGA_SR_FONTS) : VGA_SR_CMAP;
169 vgaHWRestore(pScrn, vgaReg, restore);

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