| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_vegam_smumgr.c | 1248 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1270 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1271 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1272 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1273 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1274 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1283 struct SMU75_Discrete_MCArbDramTimingTable arb_regs; local in function:vegam_program_memory_timing_parameters
1287 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1294 &arb_regs.entries[i][j]);
1303 (uint8_t *)&arb_regs,
[all...] |
| amdgpu_ci_smumgr.c | 1628 struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs
1646 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1647 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1648 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1658 SMU7_Discrete_MCArbDramTimingTable arb_regs; local in function:ci_program_memory_timing_parameters
1661 memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable));
1668 &arb_regs.entries[i][j]);
1679 (uint8_t *)&arb_regs,
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| amdgpu_fiji_smumgr.c | 1502 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
1522 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1523 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1524 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1525 arb_regs->TRRDS = (uint8_t)trrds;
1526 arb_regs->TRRDL = (uint8_t)trrdl;
1535 struct SMU73_Discrete_MCArbDramTimingTable arb_regs; local in function:fiji_program_memory_timing_parameters
1544 &arb_regs.entries[i][j]);
1554 (uint8_t *)&arb_regs,
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| amdgpu_iceland_smumgr.c | 1591 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1609 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1610 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1611 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1621 SMU71_Discrete_MCArbDramTimingTable arb_regs; local in function:iceland_program_memory_timing_parameters
1624 memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1631 &arb_regs.entries[i][j]);
1643 (uint8_t *)&arb_regs,
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| amdgpu_polaris10_smumgr.c | 1343 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1360 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1361 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1362 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1371 struct SMU74_Discrete_MCArbDramTimingTable arb_regs; local in function:polaris10_program_memory_timing_parameters
1380 &arb_regs.entries[i][j]);
1391 (const uint8_t *)&arb_regs,
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| amdgpu_tonga_smumgr.c | 1466 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1484 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1485 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1486 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1497 SMU72_Discrete_MCArbDramTimingTable arb_regs; local in function:tonga_program_memory_timing_parameters
1500 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1507 &arb_regs.entries[i][j]);
1518 (uint8_t *)&arb_regs,
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni_dpm.c | 1621 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
1626 arb_regs->mc_arb_rfsh_rate =
1635 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
1636 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
1648 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local in function:ni_do_program_memory_timing_parameters
1652 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1660 (u8 *)&arb_regs,
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| radeon_ci_dpm.c | 2531 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2545 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2546 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2547 arb_regs->McArbBurstTime = (u8)burst_time;
2555 SMU7_Discrete_MCArbDramTimingTable arb_regs; local in function:ci_do_program_memory_timing_parameters
2559 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2566 &arb_regs.entries[i][j]);
2575 (u8 *)&arb_regs,
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| radeon_si_dpm.c | 4298 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4304 arb_regs->mc_arb_rfsh_rate =
4315 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4316 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4317 arb_regs->mc_arb_burst_time = (u8)burst_time;
4328 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local in function:si_do_program_memory_timing_parameters
4332 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4339 (u8 *)&arb_regs,
4668 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local in function:si_program_ulv_memory_timing_parameters
4672 &arb_regs);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 4764 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4770 arb_regs->mc_arb_rfsh_rate =
4781 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4782 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4783 arb_regs->mc_arb_burst_time = (u8)burst_time;
4794 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local in function:si_do_program_memory_timing_parameters
4798 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4805 (u8 *)&arb_regs,
5133 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local in function:si_program_ulv_memory_timing_parameters
5137 &arb_regs);
[all...] |
