| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_clocks.c | 48 uint32_t fb_div, ref_div, post_div, sclk; local in function:radeon_legacy_get_engine_clock
78 uint32_t fb_div, ref_div, post_div, mclk; local in function:radeon_legacy_get_memory_clock
356 calc_eng_mem_clock(struct radeon_device * rdev,uint32_t req_clock,int * fb_div,int * post_div) argument
399 int fb_div, post_div; local in function:radeon_legacy_set_engine_clock
[all...] |
| H A D | radeon_legacy_crtc.c | 772 } *post_div, post_divs[] = { local in function:radeon_set_pll
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| H A D | radeon_rs780_dpm.c | 996 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + local in function:rs780_dpm_debugfs_print_current_performance_level
1019 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + local in function:rs780_dpm_get_current_sclk
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| H A D | radeon_uvd.c | 929 unsigned post_div = vco_freq / target_freq; local in function:radeon_uvd_calc_upll_post_div
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| H A D | radeon_atombios_crtc.c | 1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:atombios_crtc_set_pll
828 atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct radeon_atom_ss * ss) argument
[all...] |
| H A D | radeon_display.c | 922 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, argument
965 unsigned post_div_min, post_div_max, post_div; local in function:radeon_compute_pll_avivo
1128 uint32_t post_div; local in function:radeon_compute_pll_legacy
[all...] |
| H A D | radeon_legacy_tv.c | 861 int post_div; local in function:get_post_div
[all...] |
| H A D | radeon_mode.h | 173 uint32_t post_div; member in struct:radeon_pll
581 u32 post_div; member in struct:atom_clock_dividers
621 u32 post_div; member in struct:atom_mpll_param
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| /src/sys/arch/arm/nxp/ |
| H A D | imx_ccm_composite.c | 86 const u_int post_div = __SHIFTOUT(val, TARGET_ROOT_POST_PODF) + 1; local in function:imx_ccm_composite_get_rate
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| /src/sys/arch/mips/atheros/ |
| H A D | ar9344.c | 123 uint32_t out_div, ref_div, nint, post_div; local in function:ar9344_get_freqs
[all...] |
| /src/sys/arch/arm/sunxi/ |
| H A D | sun9i_a80_cpusclk.c | 178 const u_int post_div = __SHIFTOUT(val, CPUS_POST_DIV); local in function:sun9i_a80_cpusclk_get_rate
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nouveau_nvkm_subdev_clk_mcp77.c | 60 u32 post_div = 0; local in function:read_pll
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios.h | 30 u32 post_div; member in struct:atom_clock_dividers
70 u32 post_div; member in struct:atom_mpll_param
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| H A D | amdgpu_pll.c | 90 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, argument
133 unsigned post_div_min, post_div_max, post_div; local in function:amdgpu_pll_compute
[all...] |
| H A D | amdgpu_atombios_crtc.c | 832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:amdgpu_atombios_crtc_set_pll
582 amdgpu_atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct amdgpu_atom_ss * ss) argument
[all...] |
| H A D | amdgpu_mode.h | 198 uint32_t post_div; member in struct:amdgpu_pll
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| /src/sys/arch/arm/broadcom/ |
| H A D | bcm53xx_board.c | 325 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); local in function:bcm53xx_get_ddr_freq
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| /src/sys/dev/pci/ |
| H A D | machfb.c | 937 int post_div, dot_clock, vrefresh, vrefresh2; local in function:mach64_get_mode
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