| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFSubtarget.cpp | 28 BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU,
31 initSubtargetFeatures(CPU, FS);
32 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
43 void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
44 if (CPU == "probe")
45 CPU = sys::detail::getHostCPUNameForBPF();
46 if (CPU == "generic" || CPU == "v1")
48 if (CPU == "v2")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblySubtarget.cpp | 28 WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
33 if (CPU.empty())
34 CPU = "generic";
36 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
41 const std::string &CPU,
44 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
46 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),
|
| /src/sys/arch/hpc/conf/ |
| platid.def | 37 * CPU definitions
39 CPU:
100 CPU=MIPS_VR_4102 11 -"11" 12 -"12" 13 -"13"
104 CPU=MIPS_VR_41XX
106 CPU=MIPS_VR_4111 300 -"300"
107 CPU=MIPS_VR_4121 320 -"320"
108 CPU=MIPS_VR_4111 forDoCoMo --" MobileGearII for DoCoMo"
109 CPU=MIPS_VR_4102 mpro700 --" MobilePro 700"
110 CPU=MIPS_VR_4121 330 -"330"
113 CPU=MIPS_VR_4111 500 -"500
[all...] |
| /src/sys/arch/epoc32/stand/e32boot/ldd/ |
| cpu.h | 1 /* $NetBSD: cpu.h,v 1.1 2013/04/28 12:11:27 kiyohara Exp $ */
28 class CPU {
34 class ARM7 : public CPU {
40 class ARM7TDMI : public CPU {
46 class SA1100 : public CPU {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRSubtarget.cpp | 30 AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
32 : AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), ELFArch(0),
44 TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
46 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
50 AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
53 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCSubtarget.cpp | 27 ARCSubtarget::ARCSubtarget(const Triple &TT, const std::string &CPU,
29 : ARCGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), FrameLowering(*this),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreSubtarget.cpp | 27 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
29 : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXSubtarget.cpp | 33 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
35 // Provide the default CPU if we don't have one.
36 TargetName = std::string(CPU.empty() ? "sm_20" : CPU);
48 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
51 : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
53 TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {}
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VESubtarget.cpp | 28 VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU,
34 std::string CPUName = std::string(CPU);
39 ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPU, FS);
44 VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU,
46 : VEGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
47 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
|
| /src/external/gpl3/gdb/dist/sim/pru/ |
| interp.c | 80 /* Extract a field value from CPU register using the given REGSEL selector.
106 /* Write a value into CPU subregister pointed by reg and regsel. */
131 imem_wordaddr_to_byteaddr (SIM_CPU *cpu, uint16_t wa)
133 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
140 imem_byteaddr_to_wordaddr (SIM_CPU *cpu, uint32_t ba)
146 /* Store "nbytes" into DMEM "addr" from CPU register file, starting with
149 pru_reg2dmem (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
152 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
155 bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
159 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map local
166 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
209 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map, local
219 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map, local
542 SIM_CPU *cpu = STATE_CPU (sd, 0); local
823 SIM_CPU *cpu = STATE_CPU (sd, i); local
856 SIM_CPU *cpu = STATE_CPU (sd, 0); local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/pru/ |
| interp.c | 80 /* Extract a field value from CPU register using the given REGSEL selector.
106 /* Write a value into CPU subregister pointed by reg and regsel. */
131 imem_wordaddr_to_byteaddr (SIM_CPU *cpu, uint16_t wa)
133 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
140 imem_byteaddr_to_wordaddr (SIM_CPU *cpu, uint32_t ba)
146 /* Store "nbytes" into DMEM "addr" from CPU register file, starting with
149 pru_reg2dmem (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
152 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
155 bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
159 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map local
166 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map, local
209 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map, local
219 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map, local
542 SIM_CPU *cpu = STATE_CPU (sd, 0); local
823 SIM_CPU *cpu = STATE_CPU (sd, i); local
856 SIM_CPU *cpu = STATE_CPU (sd, 0); local
[all...] |
| /src/external/gpl3/gdb/dist/sim/m32r/ |
| m32r2.c | 58 return (((CPU (h_bpsw) & 0xc1) << 8)
59 | ((CPU (h_psw) & 0xc0) << 0)
62 return CPU (h_bbpsw) & 0xc1;
67 return CPU (h_gr[H_GR_SP]);
69 return CPU (h_cr[H_CR_SPI]);
72 return CPU (h_gr[H_GR_SP]);
74 return CPU (h_cr[H_CR_SPU]);
76 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
78 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
81 return CPU (h_cr[cr])
[all...] |
| m32rx.c | 58 return (((CPU (h_bpsw) & 0xc1) << 8)
59 | ((CPU (h_psw) & 0xc0) << 0)
62 return CPU (h_bbpsw) & 0xc1;
67 return CPU (h_gr[H_GR_SP]);
69 return CPU (h_cr[H_CR_SPI]);
72 return CPU (h_gr[H_GR_SP]);
74 return CPU (h_cr[H_CR_SPU]);
76 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
78 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
81 return CPU (h_cr[cr])
[all...] |
| cpu.c | 1 /* Misc. support for CPU family m32rbf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
100 return CPU (h_cond);
108 CPU (h_cond) = newval;
132 return CPU (h_bpsw);
140 CPU (h_bpsw) = newval;
148 return CPU (h_bbpsw)
[all...] |
| cpu2.c | 1 /* Misc. support for CPU family m32r2f.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
116 return CPU (h_cond);
124 CPU (h_cond) = newval;
148 return CPU (h_bpsw);
156 CPU (h_bpsw) = newval;
164 return CPU (h_bbpsw)
[all...] |
| cpux.c | 1 /* Misc. support for CPU family m32rxf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
116 return CPU (h_cond);
124 CPU (h_cond) = newval;
148 return CPU (h_bpsw);
156 CPU (h_bpsw) = newval;
164 return CPU (h_bbpsw)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/m32r/ |
| m32r2.c | 58 return (((CPU (h_bpsw) & 0xc1) << 8)
59 | ((CPU (h_psw) & 0xc0) << 0)
62 return CPU (h_bbpsw) & 0xc1;
67 return CPU (h_gr[H_GR_SP]);
69 return CPU (h_cr[H_CR_SPI]);
72 return CPU (h_gr[H_GR_SP]);
74 return CPU (h_cr[H_CR_SPU]);
76 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
78 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
81 return CPU (h_cr[cr])
[all...] |
| m32rx.c | 58 return (((CPU (h_bpsw) & 0xc1) << 8)
59 | ((CPU (h_psw) & 0xc0) << 0)
62 return CPU (h_bbpsw) & 0xc1;
67 return CPU (h_gr[H_GR_SP]);
69 return CPU (h_cr[H_CR_SPI]);
72 return CPU (h_gr[H_GR_SP]);
74 return CPU (h_cr[H_CR_SPU]);
76 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
78 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
81 return CPU (h_cr[cr])
[all...] |
| cpu.c | 1 /* Misc. support for CPU family m32rbf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
100 return CPU (h_cond);
108 CPU (h_cond) = newval;
132 return CPU (h_bpsw);
140 CPU (h_bpsw) = newval;
148 return CPU (h_bbpsw)
[all...] |
| cpu2.c | 1 /* Misc. support for CPU family m32r2f.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
116 return CPU (h_cond);
124 CPU (h_cond) = newval;
148 return CPU (h_bpsw);
156 CPU (h_bpsw) = newval;
164 return CPU (h_bbpsw)
[all...] |
| cpux.c | 1 /* Misc. support for CPU family m32rxf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
116 return CPU (h_cond);
124 CPU (h_cond) = newval;
148 return CPU (h_bpsw);
156 CPU (h_bpsw) = newval;
164 return CPU (h_bbpsw)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430Subtarget.cpp | 42 MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
46 StringRef CPUName = CPU;
58 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
60 : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(),
61 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| cpu.c | 1 /* Misc. support for CPU family lm32bf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
68 return CPU (h_csr[regno]);
76 CPU (h_csr[regno]) = newval;
|
| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| cpu.c | 1 /* Misc. support for CPU family lm32bf.
36 return CPU (h_pc);
44 CPU (h_pc) = newval;
52 return CPU (h_gr[regno]);
60 CPU (h_gr[regno]) = newval;
68 return CPU (h_csr[regno]);
76 CPU (h_csr[regno]) = newval;
|
| /src/sys/arch/sh3/include/ |
| endian_machdep.h | 4 # error Define SH target CPU endian-ness in port-specific header file.
|
