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  /src/usr.sbin/gspa/gspa/
gsp_pseu.c 45 pseudo(int code, operand ops)
54 if( ops == NULL )
56 if( ops->type != EXPR ){
60 if( !eval_expr(ops->op_u.value, &val, &ln) ){
75 if( ops == NULL )
77 if( ops->type != EXPR ){
81 do_asg(label, ops->op_u.value, 0);
86 if( ops == NULL )
88 for( o = ops; o != NULL; o = o->next ){
109 if( ops == NULL
    [all...]
  /src/sys/dev/onewire/
onewire_bitbang.c 78 onewire_bb_reset(const struct onewire_bbops *ops, void *arg)
84 ops->bb_tx(arg);
85 ops->bb_set(arg, 0);
87 ops->bb_set(arg, 1);
88 ops->bb_rx(arg);
91 if ((rv = ops->bb_get(arg)) == 0)
112 ops->bb_tx(arg);
113 ops->bb_set(arg, 1);
130 onewire_bb_write_bit(const struct onewire_bbops *ops, void *arg, int value)
143 ops->bb_set(arg, 0)
    [all...]
  /src/sys/dev/wscons/
wsemulconf.c 47 const struct wsemul_ops *ops; member in struct:wsemulentry
69 const struct wsemul_ops **ops; local in function:wsemul_pick
82 if (!strcmp(name, wep->ops->name)) {
84 return wep->ops;
87 for (ops = &wsemul_conf[0]; *ops != NULL; ops++)
88 if (strcmp(name, (*ops)->name) == 0)
91 return (*ops);
95 wsemul_drop(const struct wsemul_ops *ops)
    [all...]
  /src/sys/dev/mii/
mii_bitbang.c 48 ops->mbo_write(sc, (x)); \
52 #define READ ops->mbo_read(sc)
54 #define MDO ops->mbo_bits[MII_BIT_MDO]
55 #define MDI ops->mbo_bits[MII_BIT_MDI]
56 #define MDC ops->mbo_bits[MII_BIT_MDC]
57 #define MDIRPHY ops->mbo_bits[MII_BIT_DIR_HOST_PHY]
58 #define MDIRHOST ops->mbo_bits[MII_BIT_DIR_PHY_HOST]
66 mii_bitbang_sync(device_t sc, mii_bitbang_ops_t ops)
86 mii_bitbang_sendbits(device_t sc, mii_bitbang_ops_t ops, uint32_t data,
112 mii_bitbang_readreg(device_t sc, mii_bitbang_ops_t ops, int phy, int reg
    [all...]
  /src/sys/dev/i2c/
i2c_bitbang.c 51 #define SETBITS(x) ops->ibo_set_bits(v, (x))
52 #define DIR(x) ops->ibo_set_dir(v, (x))
53 #define READ ops->ibo_read_bits(v)
55 #define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */
56 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
57 #define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */
58 #define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */
67 i2c_wait_for_scl(void *v, i2c_bitbang_ops_t ops)
76 i2c_bitbang_send_stop(v, 0, ops);
84 i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops)
    [all...]
  /src/sys/fs/v7fs/
v7fs_endian.c 160 struct endian_conversion_ops *ops = &fs->val; local in function:v7fs_endian_init
166 ops->conv32 = val32_normal_order;
167 ops->conv16 = val16_normal_order;
168 ops->conv24read = val24_normal_order_read;
169 ops->conv24write = val24_normal_order_write;
172 ops->conv32 = val32_reverse_order;
173 ops->conv16 = val16_reverse_order;
174 ops->conv24read = val24_reverse_order_read;
175 ops->conv24write = val24_reverse_order_write;
178 ops->conv32 = val32_pdp_to_little
    [all...]
  /src/sys/dev/pci/ixgbe/
ixgbe_api.c 75 if (hw->mac.ops.get_rtrup2tc)
76 hw->mac.ops.get_rtrup2tc(hw, map);
239 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
252 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
268 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
282 if (hw->mac.ops.enable_relaxed_ordering)
283 hw->mac.ops.enable_relaxed_ordering(hw);
295 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
307 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
323 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr
    [all...]
ixgbe_x540.c 79 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
80 eeprom->ops.read = ixgbe_read_eerd_X540;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
82 eeprom->ops.write = ixgbe_write_eewr_X540;
83 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
84 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
85 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
86 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
89 phy->ops.init = ixgbe_init_phy_ops_generic;
90 phy->ops.reset = NULL
    [all...]
ixgbe_x550.c 72 mac->ops.dmac_config = ixgbe_dmac_config_X550;
73 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
74 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
75 mac->ops.setup_eee = NULL;
76 mac->ops.set_source_address_pruning =
78 mac->ops.set_ethertype_anti_spoofing =
81 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
82 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
83 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
84 eeprom->ops.read = ixgbe_read_ee_hostif_X550
    [all...]
ixgbe_82598.c 137 phy->ops.init = ixgbe_init_phy_ops_82598;
140 mac->ops.start_hw = ixgbe_start_hw_82598;
141 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;
142 mac->ops.reset_hw = ixgbe_reset_hw_82598;
143 mac->ops.get_media_type = ixgbe_get_media_type_82598;
144 mac->ops.get_supported_physical_layer =
146 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
147 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
148 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
149 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598
    [all...]
  /src/sys/arch/hpcmips/dev/
mq200machdep.c 63 static void mq200_setupregs(struct mq200_softc *sc, u_int32_t *ops);
211 mq200_setupregs(struct mq200_softc *sc, u_int32_t *ops)
216 switch (ops[0] & 0x3) {
219 mq200_write(sc, ops[0], ops[1]);
221 reg = mq200_read(sc, ops[0]);
222 reg = (reg & ~mask) | (ops[1] & mask);
223 mq200_write(sc, ops[0], reg);
227 switch (ops[0]) {
231 mask = ops[1]
    [all...]
  /src/sys/dev/pci/igc/
igc_api.c 27 if (hw->mac.ops.init_params) {
28 ret_val = hw->mac.ops.init_params(hw);
53 if (hw->nvm.ops.init_params) {
54 ret_val = hw->nvm.ops.init_params(hw);
79 if (hw->phy.ops.init_params) {
80 ret_val = hw->phy.ops.init_params(hw);
225 if (hw->mac.ops.update_mc_addr_list)
226 hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
241 if (hw->mac.ops.check_for_link)
242 return hw->mac.ops.check_for_link(hw)
    [all...]
igc_phy.c 28 phy->ops.init_params = igc_null_ops_generic;
29 phy->ops.acquire = igc_null_ops_generic;
30 phy->ops.check_reset_block = igc_null_ops_generic;
31 phy->ops.force_speed_duplex = igc_null_ops_generic;
32 phy->ops.get_info = igc_null_ops_generic;
33 phy->ops.set_page = igc_null_set_page;
34 phy->ops.read_reg = igc_null_read_reg;
35 phy->ops.read_reg_locked = igc_null_read_reg;
36 phy->ops.read_reg_page = igc_null_read_reg;
37 phy->ops.release = igc_null_phy_generic
    [all...]
igc_base.c 34 return hw->mac.ops.acquire_swfw_sync(hw, mask);
53 hw->mac.ops.release_swfw_sync(hw, mask);
85 ret_val = mac->ops.setup_link(hw);
109 if (!(phy->ops.check_reset_block))
113 if (phy->ops.check_reset_block(hw))
  /src/sys/arch/sun68k/stand/libsa/
promdev.c 66 struct boottab *ops; local in function:prom_iopen
73 ops = si->si_boottab;
74 dip = ops->b_devinfo;
78 DPRINTF("Boot device type: %s", ops->b_desc);
118 error = (*ops->b_open)(si);
123 ops->b_desc, error);
137 struct boottab *ops; local in function:prom_iclose
142 ops = si->si_boottab;
145 (*ops->b_close)(si);
  /src/sys/dev/fdt/
fdt_console.h 40 const struct fdt_console *ops; member in struct:fdt_console_info
48 .ops = (_ops) \
  /src/usr.bin/xlint/lint1/
ckgetopt.c 90 && tn->u.ops.right->tn_op == CON
91 && tn->u.ops.right->u.value.v_tspec == INT
92 && tn->u.ops.right->u.value.u.integer == -1
94 && tn->u.ops.left->tn_op == ASSIGN
95 && tn->u.ops.left->u.ops.right->tn_op == CALL
96 && (call = tn->u.ops.left->u.ops.right->u.call)->func->tn_op == ADDR
97 && call->func->u.ops.left->tn_op == NAME
98 && strcmp(call->func->u.ops.left->u.sym->s_name, "getopt") ==
    [all...]
ckctype.c 102 for (on = arg; on->tn_op == CVT; on = on->u.ops.left)
137 ln->u.ops.left != NULL &&
138 ln->u.ops.left->tn_op == LOAD &&
139 ln->u.ops.left->u.ops.left != NULL &&
140 ln->u.ops.left->u.ops.left->tn_op == NAME &&
141 is_ctype_table(ln->u.ops.left->u.ops.left->u.sym->s_name))
  /src/bin/dd/
dd.h 59 #define ddop_open(dir, a1, a2, ...) dir.ops->op_open(a1, a2, __VA_ARGS__)
60 #define ddop_close(dir, a1) dir.ops->op_close(a1)
61 #define ddop_fcntl(dir, a1, a2, ...) dir.ops->op_fcntl(a1, a2, __VA_ARGS__)
62 #define ddop_ioctl(dir, a1, a2, ...) dir.ops->op_ioctl(a1, a2, __VA_ARGS__)
63 #define ddop_fsync(dir, a1) dir.ops->op_fsync(a1)
64 #define ddop_ftruncate(dir, a1, a2) dir.ops->op_ftruncate(a1, a2)
65 #define ddop_lseek(dir, a1, a2, a3) dir.ops->op_lseek(a1, a2, a3)
66 #define ddop_read(dir, a1, a2, a3) dir.ops->op_read(a1, a2, a3)
67 #define ddop_write(dir, a1, a2, a3) dir.ops->op_write(a1, a2, a3)
86 struct ddfops const *ops; /* ops to use with fd * member in struct:__anona918b54a0108
    [all...]
  /src/lib/libc/rpc/
xdr_sizeof.c 145 struct xdr_ops ops; local in function:xdr_sizeof
151 ops.x_putlong = x_putlong;
152 ops.x_putbytes = x_putbytes;
153 ops.x_inline = x_inline;
154 ops.x_getpostn = x_getpostn;
155 ops.x_setpostn = x_setpostn;
156 ops.x_destroy = x_destroy;
159 ops.x_getlong = (dummyfunc1) harmless;
160 ops.x_getbytes = (dummyfunc2) harmless;
163 x.x_ops = &ops;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_sw_fence_work.c 16 if (f->ops->release)
17 f->ops->release(f);
26 err = f->ops->work(f);
69 return f->ops->name ?: "work";
90 const struct dma_fence_work_ops *ops)
92 f->ops = ops;
i915_sw_fence_work.h 34 const struct dma_fence_work_ops *ops; member in struct:dma_fence_work
38 const struct dma_fence_work_ops *ops);
  /src/sys/dev/tprof/
tprof_x86.c 57 const tprof_backend_ops_t *ops; local in function:tprof_x86_init
64 ops = &tprof_amd_ops;
68 ops = &tprof_intel_ops;
74 ncounters = ops->tbo_ncounters();
78 return tprof_backend_register(name, ops, TPROF_BACKEND_VERSION);
  /src/sys/arch/arm/nvidia/
tegra_xusbpad.c 45 tegra_xusbpad_register(device_t dev, const struct tegra_xusbpad_ops *ops)
47 KASSERT(dev != NULL && ops != NULL);
51 xusbpad_ops = ops;
  /src/lib/libkvm/
kvm_m68k.h 40 struct kvm_ops *ops; /* ops vector */ member in struct:vmstate

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