1 /* $Id: ar5312reg.h,v 1.4 2011/07/07 05:06:44 matt Exp $ */ 2 /* 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 43 #ifndef _MIPS_ATHEROS_AR5312REG_H_ 44 #define _MIPS_ATHEROS_AR5312REG_H_ 45 46 #define AR5312_MEM0_BASE 0x00000000 /* sdram */ 47 #define AR5312_MEM1_BASE 0x08000000 /* sdram/flash */ 48 #define AR5312_MEM3_BASE 0x10000000 /* flash */ 49 #define AR5312_WLAN0_BASE 0x18000000 50 #define AR5312_ENET0_BASE 0x18100000 51 #define AR5312_ENET1_BASE 0x18200000 52 #define AR5312_SDRAMCTL_BASE 0x18300000 53 #define AR5312_FLASHCTL_BASE 0x18400000 54 #define AR5312_WLAN1_BASE 0x18500000 55 #define AR5312_UART0_BASE 0x1C000000 /* high speed */ 56 #define AR5312_UART1_BASE 0x1C001000 57 #define AR5312_GPIO_BASE 0x1C002000 58 #define AR5312_SYSREG_BASE 0x1C003000 59 #define AR5312_UARTDMA_BASE 0x1C004000 60 #define AR5312_FLASH_BASE 0x1E000000 61 #define AR5312_FLASH_END 0x20000000 /* possibly aliased */ 62 63 /* 64 * FLASHCTL registers -- offset relative to AR531X_FLASHCTL_BASE 65 */ 66 #define AR5312_FLASHCTL_0 0x00 67 #define AR5312_FLASHCTL_1 0x04 68 #define AR5312_FLASHCTL_2 0x08 69 70 #define AR5312_FLASHCTL_IDCY __BITS(0,3) /* idle cycle turn */ 71 #define AR5312_FLASHCTL_WST1 __BITS(5,9) /* wait state 1 */ 72 #define AR5312_FLASHCTL_RBLE __BIT(10) /* rd byte enable */ 73 #define AR5312_FLASHCTL_WST2 __BITS(11,15) /* wait state 1 */ 74 #define AR5312_FLASHCTL_AC __BITS(16,18) /* addr chk */ 75 #define AR5312_FLASHCTL_AC_128K 0 76 #define AR5312_FLASHCTL_AC_256K 1 77 #define AR5312_FLASHCTL_AC_512K 2 78 #define AR5312_FLASHCTL_AC_1M 3 79 #define AR5312_FLASHCTL_AC_2M 4 80 #define AR5312_FLASHCTL_AC_4M 5 81 #define AR5312_FLASHCTL_AC_8M 6 82 #define AR5312_FLASHCTL_AC_16M 7 83 #define AR5312_FLASHCTL_E __BIT(19) /* enable */ 84 #define AR5312_FLASHCTL_BUSERR __BIT(24) /* buserr */ 85 #define AR5312_FLASHCTL_WPERR __BIT(25) /* wperr */ 86 #define AR5312_FLASHCTL_WP __BIT(26) /* wp */ 87 #define AR5312_FLASHCTL_BM __BIT(27) /* bm */ 88 #define AR5312_FLASHCTL_MW __BITS(28,29) /* mem width */ 89 #define AR5312_FLASHCTL_AT __BITS(31,30) /* access type */ 90 91 /* 92 * SYSREG registers -- offset relative to AR531X_SYSREG_BASE 93 */ 94 #define AR5312_SYSREG_TIMER 0x0000 95 #define AR5312_SYSREG_TIMER_RELOAD 0x0004 96 #define AR5312_SYSREG_WDOG_CTL 0x0008 97 #define AR5312_SYSREG_WDOG_TIMER 0x000c 98 #define AR5312_SYSREG_MISC_INTSTAT 0x0010 99 #define AR5312_SYSREG_MISC_INTMASK 0x0014 100 #define AR5312_SYSREG_INTSTAT 0x0018 101 #define AR5312_SYSREG_RESETCTL 0x0020 102 #define AR5312_SYSREG_CLOCKCTL 0x0064 103 #define AR5312_SYSREG_SCRATCH 0x006c 104 #define AR5312_SYSREG_AHBPERR 0x0070 105 #define AR5312_SYSREG_AHBDMAE 0x0078 106 #define AR5312_SYSREG_ENABLE 0x0080 107 #define AR5312_SYSREG_REVISION 0x0090 108 109 /* WDOG_CTL watchdog control bits */ 110 #define AR5312_WDOG_CTL_IGNORE 0x0000 111 #define AR5312_WDOG_CTL_NMI 0x0001 112 #define AR5312_WDOG_CTL_RESET 0x0002 113 114 /* Resets */ 115 #define AR5312_RESET_SYSTEM __BIT(0) 116 #define AR5312_RESET_CPU __BIT(1) 117 #define AR5312_RESET_WLAN0 __BIT(2) /* mac & bb */ 118 #define AR5312_RESET_PHY0 __BIT(3) /* enet phy */ 119 #define AR5312_RESET_PHY1 __BIT(4) /* enet phy */ 120 #define AR5312_RESET_ENET0 __BIT(5) /* mac */ 121 #define AR5312_RESET_ENET1 __BIT(6) /* mac */ 122 #define AR5312_RESET_UART0 __BIT(8) /* mac */ 123 #define AR5312_RESET_WLAN1 __BIT(9) /* mac & bb */ 124 #define AR5312_RESET_APB __BIT(10) /* bridge */ 125 #define AR5312_RESET_WARM_CPU __BIT(16) 126 #define AR5312_RESET_WARM_WLAN0_MAC __BIT(17) 127 #define AR5312_RESET_WARM_WLAN0_BB __BIT(18) 128 #define AR5312_RESET_NMI __BIT(20) 129 #define AR5312_RESET_WARM_WLAN1_MAC __BIT(21) 130 #define AR5312_RESET_WARM_WLAN1_BB __BIT(22) 131 #define AR5312_RESET_LOCAL_BUS __BIT(23) 132 #define AR5312_RESET_WDOG __BIT(24) 133 134 /* AR5312/2312 clockctl bits */ 135 #define AR5312_CLOCKCTL_PREDIVIDE __BITS(4,5) 136 #define AR5312_CLOCKCTL_MULTIPLIER __BITS(8,12) 137 #define AR5312_CLOCKCTL_DOUBLER __BIT(16) 138 139 /* AR2313 clockctl */ 140 #define AR2313_CLOCKCTL_PREDIVIDE __BITS(12,13) 141 #define AR2313_CLOCKCTL_MULTIPLIER __BITS(16,20) 142 143 /* Enables */ 144 #define AR5312_ENABLE_WLAN0 __BIT(0) 145 #define AR5312_ENABLE_ENET0 __BIT(1) 146 #define AR5312_ENABLE_ENET1 __BIT(2) 147 #define AR5312_ENABLE_WLAN1 __BITS(7,8) /* both DMA and PIO */ 148 149 /* Revision ids */ 150 #define AR5312_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf) 151 #define AR5312_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf) 152 #define AR5312_REVISION_WMAC(x) (((x) >> 8) & 0xff) 153 #define AR5312_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 154 #define AR5312_REVISION_MINOR(x) (((x) >> 0) & 0xf) 155 156 #define AR5312_REVISION_MAJ_AR5311 0x1 157 #define AR5312_REVISION_MAJ_AR5312 0x4 158 #define AR5312_REVISION_MAJ_AR2313 0x5 159 #define AR5312_REVISION_MAJ_AR5315 0xB 160 161 /* 162 * SDRAMCTL registers -- offset relative to SDRAMCTL 163 */ 164 #define AR5312_SDRAMCTL_MEM_CFG0 0x0000 165 #define AR5312_SDRAMCTL_MEM_CFG1 0x0004 166 167 /* memory config 1 bits */ 168 #define AR5312_MEM_CFG1_BANK0 __BITS(8,10) 169 #define AR5312_MEM_CFG1_BANK1 __BITS(12,15) 170 171 /* helper macro for accessing system registers without bus space */ 172 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 173 #define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE) 174 #define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v) 175 #define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE) 176 #define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v) 177 178 /* 179 * Interrupts. 180 */ 181 #define AR5312_IRQ_WLAN0 0 182 #define AR5312_IRQ_ENET0 1 183 #define AR5312_IRQ_ENET1 2 184 #define AR5312_IRQ_WLAN1 3 185 #define AR5312_IRQ_MISC 4 186 187 #define AR5312_MISC_IRQ_TIMER 0 188 #define AR5312_MISC_IRQ_AHBPERR 1 189 #define AR5312_MISC_IRQ_AHBDMAE 2 190 #define AR5312_MISC_IRQ_GPIO 3 191 #define AR5312_MISC_IRQ_UART0 4 192 #define AR5312_MISC_IRQ_UART0_DMA 5 193 #define AR5312_MISC_IRQ_WDOG 6 194 195 /* 196 * Board data. This is located in flash somewhere, ar531x_board_info 197 * locates it. 198 */ 199 #include <ah_soc.h> /* XXX really doesn't belong in hal */ 200 201 /* XXX write-around for now */ 202 #define AR5312_BOARD_MAGIC AR531X_BD_MAGIC 203 204 /* config bits */ 205 #define AR5312_BOARD_CONFIG_ENET0 BD_ENET0 206 #define AR5312_BOARD_CONFIG_ENET1 BD_ENET1 207 #define AR5312_BOARD_CONFIG_UART1 BD_UART1 208 #define AR5312_BOARD_CONFIG_UART0 BD_UART0 209 #define AR5312_BOARD_CONFIG_RSTFACTORY BD_RSTFACTORY 210 #define AR5312_BOARD_CONFIG_SYSLED BD_SYSLED 211 #define AR5312_BOARD_CONFIG_EXTUARTCLK BD_EXTUARTCLK 212 #define AR5312_BOARD_CONFIG_CPUFREQ BD_CPUFREQ 213 #define AR5312_BOARD_CONFIG_SYSFREQ BD_SYSFREQ 214 #define AR5312_BOARD_CONFIG_WLAN0 BD_WLAN0 215 #define AR5312_BOARD_CONFIG_MEMCAP BD_MEMCAP 216 #define AR5312_BOARD_CONFIG_DISWDOG BD_DISWATCHDOG 217 #define AR5312_BOARD_CONFIG_WLAN1 BD_WLAN1 218 #define AR5312_BOARD_CONFIG_AR2312 BD_ISCASPER 219 #define AR5312_BOARD_CONFIG_WLAN0_2G BD_WLAN0_2G_EN 220 #define AR5312_BOARD_CONFIG_WLAN0_5G BD_WLAN0_5G_EN 221 #define AR5312_BOARD_CONFIG_WLAN1_2G BD_WLAN1_2G_EN 222 #define AR5312_BOARD_CONFIG_WLAN1_5G BD_WLAN1_5G_EN 223 224 #endif /* _MIPS_ATHEROS_AR531XREG_H_ */ 225
Indexes created Tue Sep 23 01:09:51 GMT 2025