| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 67 #define CSR_WRITE_2(sc, reg, val) \
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| fxp.c | 91 #define CSR_WRITE_2(l, r, v) out16rb((l)->iobase+(r), (v))
418 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
420 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
423 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
433 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
444 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
446 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
453 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
456 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
470 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS)
[all...] |
| kse.c | 50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
151 CSR_WRITE_2(l, CIDR, 1);
264 CSR_WRITE_2(l, P1CR4, val);
|
| pcn.c | 50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
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| nvt.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
232 CSR_WRITE_2(l, VR_ISR, ~0);
233 CSR_WRITE_2(l, VR_IEN, 0);
366 CSR_WRITE_2(l, VR_MIIDATA, data);
|
| rge.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
220 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE);
227 CSR_WRITE_2(l, RGE_ISR, ~0);
228 CSR_WRITE_2(l, RGE_IMR, 0);
|
| stg.c | 43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
192 CSR_WRITE_2(l, STGE_EepromCtrl,
231 CSR_WRITE_2(l, STGE_IntEnable, 0);
232 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast |
238 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE);
244 CSR_WRITE_2(l, STGE_DebugCtrl,
246 CSR_WRITE_2(l, STGE_DebugCtrl,
248 CSR_WRITE_2(l, STGE_DebugCtrl,
|
| skg.c | 48 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
221 CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET);
222 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET);
223 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_SET);
225 CSR_WRITE_2(l, SK_CSR, CSR_SW_UNRESET);
227 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_UNRESET);
228 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_CLEAR);
247 CSR_WRITE_2(l, YUKON_SA1 + i * 4,
323 CSR_WRITE_2(l, YUKON_GPCR, reg);
403 CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg)
[all...] |
| vge.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
294 CSR_WRITE_2(l, VR_RDCSIZE, NRXDESC - 1);
295 CSR_WRITE_2(l, VR_RBRDU, NRXDESC - 1);
297 CSR_WRITE_2(l, VR_TDCSIZE, 0);
302 CSR_WRITE_2(l, VR_TDCSR, 01);
330 CSR_WRITE_2(l, VR_TDCSR, 04);
448 CSR_WRITE_2(l, VR_MIIDATA, data);
|
| /src/sys/dev/ic/ |
| anvar.h | 50 #define CSR_WRITE_2(sc, reg, val) \
|
| i82557var.h | 360 #define CSR_WRITE_2(sc, reg, val) \
|
| wivar.h | 233 #define CSR_WRITE_2(sc, reg, val) \
255 #define CSR_WRITE_2(sc, reg, val) \
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| rtl81x9var.h | 280 #define CSR_WRITE_2(sc, reg, val) \
|
| com.c | 147 #define CSR_WRITE_2(r, o, v) \
1829 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
2580 CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
|
| bwivar.h | 89 #define CSR_WRITE_2(sc, reg, val) \
97 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
102 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
107 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
|
| /src/sys/dev/pci/ |
| if_vtevar.h | 154 #define CSR_WRITE_2(_sc, reg, val) \
|
| if_vr.c | 288 #define CSR_WRITE_2(sc, reg, val) \
337 CSR_WRITE_2(sc, reg, \
341 CSR_WRITE_2(sc, reg, \
926 CSR_WRITE_2(sc, VR_IMR, 0x0000);
931 CSR_WRITE_2(sc, VR_ISR, status);
989 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1266 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START |
1271 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1272 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1402 CSR_WRITE_2(sc, VR_IMR, 0x0000)
[all...] |
| if_ipwreg.h | 325 #define CSR_WRITE_2(sc, reg, val) \
345 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
| if_stge.c | 225 #define CSR_WRITE_2(_sc, reg, val) \
1174 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1610 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
1617 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
1638 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
1639 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1653 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
1654 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
1659 CSR_WRITE_2(sc, STGE_MaxFrameSize,
1680 CSR_WRITE_2(sc, STGE_DebugCtrl
[all...] |
| if_vge.c | 262 #define CSR_WRITE_2(sc, reg, val) \
277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
521 CSR_WRITE_2(sc, VGE_MIIDATA, val);
1358 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1715 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1806 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
1809 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
1810 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
1817 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0)
[all...] |
| if_iwireg.h | 549 #define CSR_WRITE_2(sc, reg, val) \
569 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
|
| if_kse.c | 71 #define CSR_WRITE_2(sc, off, val) \
451 CSR_WRITE_2(sc, SIDER, 1);
802 CSR_WRITE_2(sc, SGCR3, i | CR3_USEFC);
878 CSR_WRITE_2(sc, GRR, 1);
880 CSR_WRITE_2(sc, GRR, 0);
883 CSR_WRITE_2(sc, SIDER, 1);
1356 CSR_WRITE_2(sc, P1CR4, p1cr4);
1436 CSR_WRITE_2(sc, phy1csr[reg], val);
1509 CSR_WRITE_2(sc, IACR, reg);
1525 CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p)
[all...] |
| if_agereg.h | 856 #define CSR_WRITE_2(sc, reg, val) \
|
| if_alereg.h | 953 #define CSR_WRITE_2(_sc, reg, val) \
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| dm9000.c | 155 CSR_WRITE_2(struct local *l, int reg, int data)
308 CSR_WRITE_2(l, MWCMD, val);
|
