| /src/sys/arch/sandpoint/stand/altboot/ |
| siisata.c | 42 #define CSR_WRITE_4(r,v) out32rb(r,v)
180 CSR_WRITE_4(sc, val | 01); /* perform init */
182 CSR_WRITE_4(sc, val);
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| dsk.c | 58 #define CSR_WRITE_4(r,v) out32rb(r,v)
|
| fxp.c | 93 #define CSR_WRITE_4(l, r, v) out32rb((l)->iobase+(r), (v))
202 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
220 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
276 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cbp));
299 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cb_ias));
320 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(rfa));
351 CSR_WRITE_4(l, FXP_CSR_SCB_GENERAL, VTOPHYS(txd));
517 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
|
| kse.c | 48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
177 CSR_WRITE_4(l, TDLB, VTOPHYS(txd));
178 CSR_WRITE_4(l, RDLB, VTOPHYS(rxd));
179 CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */
180 CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */
181 CSR_WRITE_4(l, MDRSC, 01); /* start receiving */
199 CSR_WRITE_4(l, MDTSC, 01); /* start transmission */
241 CSR_WRITE_4(l, MDRSC, 01); /* restart receiving */
254 CSR_WRITE_4(l, MDRSC, 01); /* necessary? */
|
| pcn.c | 48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
160 CSR_WRITE_4(l, PCN_RDP, 0);
313 CSR_WRITE_4(l, PCN_RAP, r);
320 CSR_WRITE_4(l, PCN_RAP, r);
321 CSR_WRITE_4(l, PCN_RDP, v);
327 CSR_WRITE_4(l, PCN_RAP, r);
334 CSR_WRITE_4(l, PCN_RAP, r);
335 CSR_WRITE_4(l, PCN_BDP, v);
|
| nvt.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
228 CSR_WRITE_4(l, VR_RDBA, VTOPHYS(rxd));
229 CSR_WRITE_4(l, VR_TDBA, VTOPHYS(txd));
|
| rge.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
173 CSR_WRITE_4(l, RGE_IDR0, reg);
175 CSR_WRITE_4(l, RGE_IDR4, reg);
221 CSR_WRITE_4(l, RGE_TCR, l->tcr);
222 CSR_WRITE_4(l, RGE_RCR, l->rcr);
223 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd));
224 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd));
225 CSR_WRITE_4(l, RGE_TNPDS + 4, 0);
226 CSR_WRITE_4(l, RGE_RDSAR + 4, 0);
319 CSR_WRITE_4(l, RGE_PHYAR, v)
[all...] |
| stg.c | 45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
234 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0);
235 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd));
236 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0);
237 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd));
239 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */
272 CSR_WRITE_4(l, STGE_MACCtrl, macctl);
302 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow);
364 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset |
|
| skg.c | 50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
229 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */
252 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON);
254 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON);
274 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET);
275 CSR_WRITE_4(l, SK_RXRB1_START, 0);
276 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0);
277 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0);
278 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff);
279 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_ON)
[all...] |
| vge.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
293 CSR_WRITE_4(l, VR_RDB, VTOPHYS(rxd));
296 CSR_WRITE_4(l, VR_TDB0, VTOPHYS(txd));
307 CSR_WRITE_4(l, VR_ISR, ~0);
308 CSR_WRITE_4(l, VR_IEN, 0);
|
| /src/sys/arch/arm/xscale/ |
| pxa2x0_i2c.c | 408 #define CSR_WRITE_4(sc,r,v) bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v)
420 CSR_WRITE_4(sc, I2C_ICR, ICR_UR);
421 CSR_WRITE_4(sc, I2C_ISAR, 0);
422 CSR_WRITE_4(sc, I2C_ISR, ISR_ALL);
425 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr);
449 CSR_WRITE_4(sc, I2C_ISR, isr);
458 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START);
467 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_STOP);
483 CSR_WRITE_4(sc, I2C_IDBR, (addr << 1) | rd_req);
484 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START | ICR_TB)
[all...] |
| ixp425_pci_space.c | 53 #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \
270 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
271 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
274 CSR_WRITE_4(PCI_ISR, ISR_PFE);
290 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
291 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
294 CSR_WRITE_4(PCI_ISR, ISR_PFE);
307 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
308 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
311 CSR_WRITE_4(PCI_ISR, ISR_PFE)
[all...] |
| pxa2x0_mci.c | 151 #define CSR_WRITE_4(sc, reg, val) \
154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
173 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
184 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
358 CSR_WRITE_4(sc, MMC_SPI, 0);
359 CSR_WRITE_4(sc, MMC_RESTO, 0x7f);
360 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
511 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt);
512 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START)
[all...] |
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 69 #define CSR_WRITE_4(sc, reg, val) \
|
| /src/sys/dev/ic/ |
| i82557var.h | 362 #define CSR_WRITE_4(sc, reg, val) \
|
| wivar.h | 230 #define CSR_WRITE_4(sc, reg, val) \
252 #define CSR_WRITE_4(sc, reg, val) \
|
| rtl81x9var.h | 278 #define CSR_WRITE_4(sc, reg, val) \
|
| /src/sys/dev/pci/ |
| if_vr.c | 286 #define CSR_WRITE_4(sc, reg, val) \
345 CSR_WRITE_4(sc, reg, \
349 CSR_WRITE_4(sc, reg, \
478 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
479 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
484 CSR_WRITE_4(sc, VR_MAR0, 0);
485 CSR_WRITE_4(sc, VR_MAR1, 0);
515 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
516 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
823 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr))
[all...] |
| if_bgevar.h | 100 #define CSR_WRITE_4(sc, reg, val) \
108 CSR_WRITE_4(sc, reg, val); \
113 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
120 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
|
| if_ipwreg.h | 328 #define CSR_WRITE_4(sc, reg, val) \
339 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
344 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
349 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
350 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
354 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
|
| if_stge.c | 223 #define CSR_WRITE_4(_sc, reg, val) \
997 CSR_WRITE_4(sc, STGE_DMACtrl,
1487 CSR_WRITE_4(sc, STGE_AsicCtrl,
1576 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
1577 CSR_WRITE_4(sc, STGE_StatisticsMask,
1589 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
1591 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
1594 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
1596 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
1630 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl
[all...] |
| if_vge.c | 260 #define CSR_WRITE_4(sc, reg, val) \
279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))
286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))
650 CSR_WRITE_4(sc, VGE_MAR0, 0);
651 CSR_WRITE_4(sc, VGE_MAR1, 0);
660 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
661 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
711 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
712 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
1476 CSR_WRITE_4(sc, VGE_ISR, status)
[all...] |
| if_iwireg.h | 552 #define CSR_WRITE_4(sc, reg, val) \
563 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
568 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
573 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
574 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
578 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
|
| if_kse.c | 67 #define CSR_WRITE_4(sc, off, val) \
764 CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0));
765 CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0));
813 CSR_WRITE_4(sc, MDTXC, sc->sc_txc);
814 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc);
815 CSR_WRITE_4(sc, MDRSC, 1);
821 CSR_WRITE_4(sc, INTST, ~0);
822 CSR_WRITE_4(sc, INTEN, sc->sc_inten);
854 CSR_WRITE_4(sc, MDTXC, sc->sc_txc);
855 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc)
[all...] |
| if_etreg.h | 355 #define CSR_WRITE_4(sc, reg, val) \
|
