1 /* $NetBSD: pmap.h,v 1.180 2026/04/28 05:51:14 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #include "opt_multiprocessor.h" 79 #endif 80 #include <arm/cpufunc.h> 81 #include <arm/locore.h> 82 83 #include <sys/cpu.h> 84 85 #include <uvm/uvm_object.h> 86 87 #include <uvm/pmap/pmap_devmap.h> 88 #include <uvm/pmap/pmap_pvt.h> 89 #endif 90 91 #ifdef ARM_MMU_EXTENDED 92 #define PMAP_HWPAGEWALKER 1 93 #define PMAP_TLB_MAX 1 94 #if PMAP_TLB_MAX > 1 95 #define PMAP_TLB_NEED_SHOOTDOWN 1 96 #endif 97 #define PMAP_TLB_FLUSH_ASID_ON_RESET arm_has_tlbiasid_p 98 #define PMAP_TLB_NUM_PIDS 256 99 100 #define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1) 101 #include <uvm/pmap/tlb.h> 102 #include <uvm/pmap/pmap_tlb.h> 103 104 /* 105 * If we have an EXTENDED MMU and the address space is split evenly between 106 * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for 107 * user and kernel address spaces. 108 */ 109 #if (KERNEL_BASE & 0x80000000) == 0 110 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000 111 #endif 112 #endif /* ARM_MMU_EXTENDED */ 113 114 /* 115 * a pmap describes a processes' 4GB virtual address space. this 116 * virtual address space can be broken up into 4096 1MB regions which 117 * are described by L1 PTEs in the L1 table. 118 * 119 * There is a line drawn at KERNEL_BASE. Everything below that line 120 * changes when the VM context is switched. Everything above that line 121 * is the same no matter which VM context is running. This is achieved 122 * by making the L1 PTEs for those slots above KERNEL_BASE reference 123 * kernel L2 tables. 124 * 125 * The basic layout of the virtual address space thus looks like this: 126 * 127 * 0xffffffff 128 * . 129 * . 130 * . 131 * KERNEL_BASE 132 * -------------------- 133 * . 134 * . 135 * . 136 * 0x00000000 137 */ 138 139 /* 140 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 141 * A bucket size of 16 provides for 16MB of contiguous virtual address 142 * space per l2_dtable. Most processes will, therefore, require only two or 143 * three of these to map their whole working set. 144 */ 145 #define L2_BUCKET_XLOG2 (L1_S_SHIFT) 146 #define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2) 147 #define L2_BUCKET_LOG2 4 148 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 149 150 /* 151 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 152 * of l2_dtable structures required to track all possible page descriptors 153 * mappable by an L1 translation table is given by the following constants: 154 */ 155 #define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2)) 156 #define L2_SIZE (1 << L2_LOG2) 157 158 /* 159 * tell MI code that the cache is virtually-indexed. 160 * ARMv6 is physically-tagged but all others are virtually-tagged. 161 */ 162 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 163 #define PMAP_CACHE_VIPT 164 #else 165 #define PMAP_CACHE_VIVT 166 #endif 167 168 #ifndef _LOCORE 169 170 #ifndef ARM_MMU_EXTENDED 171 struct l1_ttable; 172 struct l2_dtable; 173 174 /* 175 * Track cache/tlb occupancy using the following structure 176 */ 177 union pmap_cache_state { 178 struct { 179 union { 180 uint8_t csu_cache_b[2]; 181 uint16_t csu_cache; 182 } cs_cache_u; 183 184 union { 185 uint8_t csu_tlb_b[2]; 186 uint16_t csu_tlb; 187 } cs_tlb_u; 188 } cs_s; 189 uint32_t cs_all; 190 }; 191 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 192 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 193 #define cs_cache cs_s.cs_cache_u.csu_cache 194 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 195 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 196 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 197 198 /* 199 * Assigned to cs_all to force cacheops to work for a particular pmap 200 */ 201 #define PMAP_CACHE_STATE_ALL 0xffffffffu 202 #endif /* !ARM_MMU_EXTENDED */ 203 204 205 #define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET) 206 #define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE) 207 #define DEVMAP_FLAGS PMAP_DEV 208 209 /* 210 * The pmap structure itself 211 */ 212 struct pmap { 213 kmutex_t pm_lock; 214 u_int pm_refs; 215 #ifndef ARM_HAS_VBAR 216 pd_entry_t *pm_pl1vec; 217 pd_entry_t pm_l1vec; 218 #endif 219 struct l2_dtable *pm_l2[L2_SIZE]; 220 struct pmap_statistics pm_stats; 221 LIST_ENTRY(pmap) pm_list; 222 bool pm_remove_all; 223 #ifdef ARM_MMU_EXTENDED 224 pd_entry_t *pm_l1; 225 paddr_t pm_l1_pa; 226 #ifdef MULTIPROCESSOR 227 kcpuset_t *pm_onproc; 228 kcpuset_t *pm_active; 229 #if PMAP_TLB_MAX > 1 230 u_int pm_shootdown_pending; 231 #endif 232 #endif 233 struct pmap_asid_info pm_pai[PMAP_TLB_MAX]; 234 #else 235 struct l1_ttable *pm_l1; 236 union pmap_cache_state pm_cstate; 237 uint8_t pm_domain; 238 bool pm_activated; 239 #endif 240 }; 241 242 struct pmap_kernel { 243 struct pmap kernel_pmap; 244 }; 245 246 /* 247 * Physical / virtual address structure. In a number of places (particularly 248 * during bootstrapping) we need to keep track of the physical and virtual 249 * addresses of various pages 250 */ 251 typedef struct pv_addr { 252 SLIST_ENTRY(pv_addr) pv_list; 253 paddr_t pv_pa; 254 vaddr_t pv_va; 255 vsize_t pv_size; 256 uint8_t pv_cache; 257 uint8_t pv_prot; 258 } pv_addr_t; 259 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 260 261 extern pv_addrqh_t pmap_freeq; 262 extern pv_addr_t kernelstack; 263 extern pv_addr_t abtstack; 264 extern pv_addr_t fiqstack; 265 extern pv_addr_t irqstack; 266 extern pv_addr_t undstack; 267 extern pv_addr_t idlestack; 268 extern pv_addr_t systempage; 269 extern pv_addr_t kernel_l1pt; 270 #if defined(EFI_RUNTIME) 271 extern pv_addr_t efirt_l1pt; 272 #endif 273 274 #ifdef ARM_MMU_EXTENDED 275 extern bool arm_has_tlbiasid_p; /* also in <arm/locore.h> */ 276 277 static inline void 278 pmap_md_asid_activate(tlb_asid_t asid, pmap_t pm, struct lwp *l) 279 { 280 KASSERT(kpreempt_disabled()); 281 282 struct cpu_info * const ci = curcpu(); 283 284 /* 285 * Assume that TTBR1 has only global mappings and TTBR0 only 286 * has non-global mappings. To prevent speculation from doing 287 * evil things translation table walks using TTBR0 are disabled 288 * whilst there is no active userland pmap. Assert this here. 289 * 290 * In doing so the new CONTEXTIDR (ASID) and new TTBR0 value are 291 * only enable once both are set. 292 */ 293 KASSERT( 294 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 295 (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 296 ); 297 298 if (pm == pmap_kernel()) 299 return; 300 301 armreg_contextidr_write(asid); 302 armreg_ttbr_write(pm->pm_l1_pa | 303 (ci->ci_mpidr ? TTBR_MPATTR : TTBR_UPATTR)); 304 isb(); 305 306 /* 307 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 308 * have been updated. 309 */ 310 const uint32_t old_ttbcr = armreg_ttbcr_read(); 311 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 312 cpu_cpwait(); 313 314 KASSERTMSG(ci->ci_pmap_asid_cur == asid, "%u vs %u", 315 ci->ci_pmap_asid_cur, asid); 316 ci->ci_pmap_cur = pm; 317 } 318 319 void 320 static inline 321 pmap_md_asid_deactivate(pmap_t pm) 322 { 323 KASSERT(kpreempt_disabled()); 324 325 struct cpu_info * const ci = curcpu(); 326 /* 327 * Disable translation table walks from TTBR0 while no pmap has been 328 * activated. 329 */ 330 const uint32_t old_ttbcr = armreg_ttbcr_read(); 331 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 332 isb(); 333 334 ci->ci_pmap_cur = pmap_kernel(); 335 } 336 #endif 337 338 /* 339 * Determine various modes for PTEs (user vs. kernel, cacheable 340 * vs. non-cacheable). 341 */ 342 #define PTE_KERNEL 0 343 #define PTE_USER 1 344 #define PTE_NOCACHE 0 345 #define PTE_CACHE 1 346 #define PTE_PAGETABLE 2 347 #define PTE_DEV 3 348 349 /* 350 * Flags that indicate attributes of pages or mappings of pages. 351 * 352 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 353 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 354 * pv_entry's for each page. They live in the same "namespace" so 355 * that we can clear multiple attributes at a time. 356 * 357 * Note the "non-cacheable" flag generally means the page has 358 * multiple mappings in a given address space. 359 */ 360 #define PVF_MOD 0x01 /* page is modified */ 361 #define PVF_REF 0x02 /* page is referenced */ 362 #define PVF_WIRED 0x04 /* mapping is wired */ 363 #define PVF_WRITE 0x08 /* mapping is writable */ 364 #define PVF_EXEC 0x10 /* mapping is executable */ 365 #ifdef PMAP_CACHE_VIVT 366 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 367 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 368 #define PVF_NC (PVF_UNC|PVF_KNC) 369 #endif 370 #ifdef PMAP_CACHE_VIPT 371 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 372 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 373 #endif 374 #define PVF_COLORED 0x80 /* page has or had a color */ 375 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 376 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 377 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 378 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 379 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 380 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 381 382 /* 383 * Commonly referenced structures 384 */ 385 extern int arm_poolpage_vmfreelist; 386 387 /* 388 * Macros that we need to export 389 */ 390 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 391 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 392 393 #define pmap_is_modified(pg) \ 394 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 395 #define pmap_is_referenced(pg) \ 396 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 397 #define pmap_is_page_colored_p(md) \ 398 (((md)->pvh_attrs & PVF_COLORED) != 0) 399 400 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 401 402 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 403 u_int arm32_mmap_flags(paddr_t); 404 #define ARM32_MMAP_WRITECOMBINE 0x40000000 405 #define ARM32_MMAP_CACHEABLE 0x20000000 406 #define ARM_MMAP_WRITECOMBINE ARM32_MMAP_WRITECOMBINE 407 #define ARM_MMAP_CACHEABLE ARM32_MMAP_CACHEABLE 408 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 409 410 #define PMAP_PTE 0x10000000 /* kenter_pa */ 411 #define PMAP_DEV 0x20000000 /* kenter_pa */ 412 #define PMAP_DEV_SO 0x40000000 /* kenter_pa */ 413 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO) 414 415 /* 416 * Functions that we need to export 417 */ 418 void pmap_procwr(struct proc *, vaddr_t, int); 419 bool pmap_remove_all(pmap_t); 420 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 421 422 #define PMAP_NEED_PROCWR 423 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 424 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 425 426 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 427 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 428 void pmap_prefer(vaddr_t, vaddr_t *, int); 429 #endif 430 431 #ifdef ARM_MMU_EXTENDED 432 int pmap_maxproc_set(int); 433 struct pmap * 434 pmap_efirt(void); 435 #endif 436 437 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 438 439 /* Functions we use internally. */ 440 #ifdef PMAP_STEAL_MEMORY 441 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 442 void pmap_boot_pageadd(pv_addr_t *); 443 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 444 #endif 445 void pmap_bootstrap(vaddr_t, vaddr_t); 446 447 struct pmap * 448 pmap_efirt(void); 449 void pmap_activate_efirt(void); 450 void pmap_deactivate_efirt(void); 451 452 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 453 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 454 int pmap_prefetchabt_fixup(void *); 455 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 456 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 457 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 458 459 void pmap_postinit(void); 460 461 void vector_page_setprot(int); 462 463 /* Bootstrapping routines. */ 464 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 465 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 466 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 467 void pmap_unmap_chunk(vaddr_t, vaddr_t, vsize_t); 468 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 469 470 vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int); 471 472 /* 473 * Special page zero routine for use by the idle loop (no cache cleans). 474 */ 475 bool pmap_pageidlezero(paddr_t); 476 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 477 478 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 479 /* 480 * For the pmap, this is a more useful way to map a direct mapped page. 481 * It returns either the direct-mapped VA or the VA supplied if it can't 482 * be direct mapped. 483 */ 484 vaddr_t pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t); 485 #endif 486 487 /* 488 * used by dumpsys to record the PA of the L1 table 489 */ 490 uint32_t pmap_kernel_L1_addr(void); 491 /* 492 * The current top of kernel VM 493 */ 494 extern vaddr_t pmap_curmaxkvaddr; 495 496 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 497 /* 498 * Ending VA of direct mapped memory (usually KERNEL_VM_BASE). 499 */ 500 extern vaddr_t pmap_directlimit; 501 #endif 502 503 /* 504 * Useful macros and constants 505 */ 506 507 /* Virtual address to page table entry */ 508 static inline pt_entry_t * 509 vtopte(vaddr_t va) 510 { 511 pd_entry_t *pdep; 512 pt_entry_t *ptep; 513 514 KASSERT(trunc_page(va) == va); 515 516 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 517 return (NULL); 518 return (ptep); 519 } 520 521 /* 522 * Virtual address to physical address 523 */ 524 static inline paddr_t 525 vtophys(vaddr_t va) 526 { 527 paddr_t pa; 528 529 if (pmap_extract(pmap_kernel(), va, &pa) == false) 530 return (0); /* XXXSCW: Panic? */ 531 532 return (pa); 533 } 534 535 /* 536 * The new pmap ensures that page-tables are always mapping Write-Thru. 537 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 538 * on every change. 539 * 540 * Unfortunately, not all CPUs have a write-through cache mode. So we 541 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 542 * and if there is the chance for PTE syncs to be needed, we define 543 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 544 * the code. 545 */ 546 extern int pmap_needs_pte_sync; 547 #if defined(_KERNEL_OPT) 548 /* 549 * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a 550 * single MMU type is selected. 551 * 552 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 553 * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs. 554 * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs. 555 * 556 * Use run time evaluation for all other cases. 557 * 558 */ 559 #if (ARM_NMMUS == 1) 560 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) 561 #define PMAP_INCLUDE_PTE_SYNC 562 #define PMAP_NEEDS_PTE_SYNC 1 563 #elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0) 564 #define PMAP_NEEDS_PTE_SYNC 0 565 #endif 566 #endif 567 #endif /* _KERNEL_OPT */ 568 569 /* 570 * Provide a fallback in case we were not able to determine it at 571 * compile-time. 572 */ 573 #ifndef PMAP_NEEDS_PTE_SYNC 574 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 575 #define PMAP_INCLUDE_PTE_SYNC 576 #endif 577 578 static inline void 579 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 580 { 581 if (PMAP_NEEDS_PTE_SYNC) { 582 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 583 #ifdef SHEEVA_L2_CACHE 584 cpu_sdcache_wb_range((vaddr_t)ptep, -1, 585 cnt * sizeof(pt_entry_t)); 586 #endif 587 } 588 dsb(sy); 589 } 590 591 #define PDE_SYNC(pdep) pmap_ptesync((pdep), 1) 592 #define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt)) 593 #define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE) 594 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 595 596 #define l1pte_valid_p(pde) ((pde) != 0) 597 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 598 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 599 && ((pde) & L1_S_V6_SUPER) != 0) 600 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 601 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 602 #define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK) 603 #define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT) 604 605 static inline void 606 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde) 607 { 608 *pdep = pde; 609 } 610 611 static inline void 612 l1pte_set(pt_entry_t *pdep, pt_entry_t pde) 613 { 614 *pdep = pde; 615 if (l1pte_page_p(pde)) { 616 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep); 617 for (int k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) { 618 pde += L2_T_SIZE; 619 pdep[k] = pde; 620 } 621 } else if (l1pte_supersection_p(pde)) { 622 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep); 623 for (int k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) { 624 pdep[k] = pde; 625 } 626 } 627 } 628 629 #define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT)) 630 #define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 631 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 632 #define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L) 633 #define l2pte_minidata_p(pte) (((pte) & \ 634 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 635 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 636 637 static inline void 638 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 639 { 640 if (l1pte_lpage_p(pte)) { 641 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 642 for (int k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) { 643 *ptep++ = pte; 644 } 645 } else { 646 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 647 for (int k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) { 648 KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte); 649 *ptep++ = pte; 650 pte += L2_S_SIZE; 651 if (opte) 652 opte += L2_S_SIZE; 653 } 654 } 655 } 656 657 static inline void 658 l2pte_reset(pt_entry_t *ptep) 659 { 660 KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 661 *ptep = 0; 662 for (int k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 663 ptep[k] = 0; 664 } 665 } 666 667 /* L1 and L2 page table macros */ 668 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 669 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 670 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 671 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 672 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 673 674 #define pmap_pte_v(pte) l2pte_valid_p(*(pte)) 675 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 676 677 static inline uint32_t 678 pte_value(pt_entry_t pte) 679 { 680 return pte; 681 } 682 683 static inline bool 684 pte_valid_p(pt_entry_t pte) 685 { 686 687 return l2pte_valid_p(pte); 688 } 689 690 691 /* Size of the kernel part of the L1 page table */ 692 #define KERNEL_PD_SIZE \ 693 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 694 695 void bzero_page(vaddr_t); 696 void bcopy_page(vaddr_t, vaddr_t); 697 698 #ifdef FPU_VFP 699 void bzero_page_vfp(vaddr_t); 700 void bcopy_page_vfp(vaddr_t, vaddr_t); 701 #endif 702 703 /************************* ARM MMU configuration *****************************/ 704 705 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 706 void pmap_copy_page_generic(paddr_t, paddr_t); 707 void pmap_zero_page_generic(paddr_t); 708 709 void pmap_pte_init_generic(void); 710 #if defined(CPU_ARM8) 711 void pmap_pte_init_arm8(void); 712 #endif 713 #if defined(CPU_ARM9) 714 void pmap_pte_init_arm9(void); 715 #endif /* CPU_ARM9 */ 716 #if defined(CPU_ARM10) 717 void pmap_pte_init_arm10(void); 718 #endif /* CPU_ARM10 */ 719 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 720 void pmap_pte_init_arm11(void); 721 #endif /* CPU_ARM11 */ 722 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 723 void pmap_pte_init_arm11mpcore(void); 724 #endif 725 #if ARM_MMU_V6 == 1 726 void pmap_pte_init_armv6(void); 727 #endif /* ARM_MMU_V6 */ 728 #if ARM_MMU_V7 == 1 729 void pmap_pte_init_armv7(void); 730 #endif /* ARM_MMU_V7 */ 731 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 732 733 #if ARM_MMU_SA1 == 1 734 void pmap_pte_init_sa1(void); 735 #endif /* ARM_MMU_SA1 == 1 */ 736 737 #if ARM_MMU_XSCALE == 1 738 void pmap_copy_page_xscale(paddr_t, paddr_t); 739 void pmap_zero_page_xscale(paddr_t); 740 741 void pmap_pte_init_xscale(void); 742 743 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 744 745 #define PMAP_UAREA(va) pmap_uarea(va) 746 void pmap_uarea(vaddr_t); 747 #endif /* ARM_MMU_XSCALE == 1 */ 748 749 extern pt_entry_t pte_l1_s_nocache_mode; 750 extern pt_entry_t pte_l2_l_nocache_mode; 751 extern pt_entry_t pte_l2_s_nocache_mode; 752 753 extern pt_entry_t pte_l1_s_cache_mode; 754 extern pt_entry_t pte_l2_l_cache_mode; 755 extern pt_entry_t pte_l2_s_cache_mode; 756 757 extern pt_entry_t pte_l1_s_cache_mode_pt; 758 extern pt_entry_t pte_l2_l_cache_mode_pt; 759 extern pt_entry_t pte_l2_s_cache_mode_pt; 760 761 extern pt_entry_t pte_l1_s_wc_mode; 762 extern pt_entry_t pte_l2_l_wc_mode; 763 extern pt_entry_t pte_l2_s_wc_mode; 764 765 extern pt_entry_t pte_l1_s_cache_mask; 766 extern pt_entry_t pte_l2_l_cache_mask; 767 extern pt_entry_t pte_l2_s_cache_mask; 768 769 extern pt_entry_t pte_l1_s_prot_u; 770 extern pt_entry_t pte_l1_s_prot_w; 771 extern pt_entry_t pte_l1_s_prot_ro; 772 extern pt_entry_t pte_l1_s_prot_mask; 773 774 extern pt_entry_t pte_l2_s_prot_u; 775 extern pt_entry_t pte_l2_s_prot_w; 776 extern pt_entry_t pte_l2_s_prot_ro; 777 extern pt_entry_t pte_l2_s_prot_mask; 778 779 extern pt_entry_t pte_l2_l_prot_u; 780 extern pt_entry_t pte_l2_l_prot_w; 781 extern pt_entry_t pte_l2_l_prot_ro; 782 extern pt_entry_t pte_l2_l_prot_mask; 783 784 extern pt_entry_t pte_l1_ss_proto; 785 extern pt_entry_t pte_l1_s_proto; 786 extern pt_entry_t pte_l1_c_proto; 787 extern pt_entry_t pte_l2_s_proto; 788 789 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 790 extern void (*pmap_zero_page_func)(paddr_t); 791 792 /* 793 * Global varaiables in cpufunc_asm_xscale.S supporting the Xscale 794 * cache clean/purge functions. 795 */ 796 extern vaddr_t xscale_minidata_clean_addr; 797 extern vsize_t xscale_minidata_clean_size; 798 extern vaddr_t xscale_cache_clean_addr; 799 extern vsize_t xscale_cache_clean_size; 800 801 #endif /* !_LOCORE */ 802 803 /*****************************************************************************/ 804 805 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 806 807 /* 808 * Definitions for MMU domains 809 */ 810 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 811 #define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */ 812 813 #ifdef ARM_MMU_EXTENDED 814 #define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */ 815 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | (DOMAIN_CLIENT << (PMAP_DOMAIN_USER*2))) 816 #else 817 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2))) 818 #endif 819 820 /* 821 * These macros define the various bit masks in the PTE. 822 * 823 * We use these macros since we use different bits on different processor 824 * models. 825 */ 826 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 827 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 828 #define L1_S_PROT_RO_generic (0) 829 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 830 831 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 832 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 833 #define L1_S_PROT_RO_xscale (0) 834 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 835 836 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 837 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 838 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 839 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 840 841 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 842 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 843 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 844 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 845 846 #define L1_S_NOCACHE_generic (0) 847 #define L1_S_NOCACHE_armv6n (L1_S_XS_TEX(1)) 848 849 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 850 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 851 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 852 #define L1_S_CACHE_MASK_armv6n (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 853 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 854 855 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 856 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 857 #define L2_L_PROT_RO_generic (0) 858 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 859 860 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 861 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 862 #define L2_L_PROT_RO_xscale (0) 863 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 864 865 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 866 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 867 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 868 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 869 870 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 871 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 872 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 873 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 874 875 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 876 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 877 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 878 #define L2_L_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 879 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 880 881 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 882 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 883 #define L2_S_PROT_RO_generic (0) 884 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 885 886 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 887 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 888 #define L2_S_PROT_RO_xscale (0) 889 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 890 891 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 892 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 893 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 894 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 895 896 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 897 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 898 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 899 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 900 901 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 902 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 903 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 904 #ifdef ARMV6_EXTENDED_SMALL_PAGE 905 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 906 #else 907 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 908 #endif 909 #define L2_S_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 910 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 911 912 913 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 914 #define L1_S_PROTO_xscale (L1_TYPE_S) 915 #define L1_S_PROTO_armv6 (L1_TYPE_S) 916 #define L1_S_PROTO_armv7 (L1_TYPE_S) 917 918 #define L1_SS_PROTO_generic 0 919 #define L1_SS_PROTO_xscale 0 920 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 921 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 922 923 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 924 #define L1_C_PROTO_xscale (L1_TYPE_C) 925 #define L1_C_PROTO_armv6 (L1_TYPE_C) 926 #define L1_C_PROTO_armv7 (L1_TYPE_C) 927 928 #define L2_L_PROTO (L2_TYPE_L) 929 930 #define L2_S_PROTO_generic (L2_TYPE_S) 931 #define L2_S_PROTO_xscale (L2_TYPE_XS) 932 #ifdef ARMV6_EXTENDED_SMALL_PAGE 933 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 934 #else 935 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 936 #endif 937 #ifdef ARM_MMU_EXTENDED 938 #define L2_S_PROTO_armv6n (L2_TYPE_S|L2_XS_XN) 939 #else 940 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 941 #endif 942 #ifdef ARM_MMU_EXTENDED 943 #define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN) 944 #else 945 #define L2_S_PROTO_armv7 (L2_TYPE_S) 946 #endif 947 948 /* 949 * User-visible names for the ones that vary with MMU class. 950 */ 951 952 #if ARM_NMMUS > 1 953 /* More than one MMU class configured; use variables. */ 954 #define L1_S_PROT_U pte_l1_s_prot_u 955 #define L1_S_PROT_W pte_l1_s_prot_w 956 #define L1_S_PROT_RO pte_l1_s_prot_ro 957 #define L1_S_PROT_MASK pte_l1_s_prot_mask 958 959 #define L2_S_PROT_U pte_l2_s_prot_u 960 #define L2_S_PROT_W pte_l2_s_prot_w 961 #define L2_S_PROT_RO pte_l2_s_prot_ro 962 #define L2_S_PROT_MASK pte_l2_s_prot_mask 963 964 #define L2_L_PROT_U pte_l2_l_prot_u 965 #define L2_L_PROT_W pte_l2_l_prot_w 966 #define L2_L_PROT_RO pte_l2_l_prot_ro 967 #define L2_L_PROT_MASK pte_l2_l_prot_mask 968 969 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 970 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 971 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 972 973 #define L1_SS_PROTO pte_l1_ss_proto 974 #define L1_S_PROTO pte_l1_s_proto 975 #define L1_C_PROTO pte_l1_c_proto 976 #define L2_S_PROTO pte_l2_s_proto 977 978 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 979 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 980 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 981 #define L1_S_PROT_U L1_S_PROT_U_generic 982 #define L1_S_PROT_W L1_S_PROT_W_generic 983 #define L1_S_PROT_RO L1_S_PROT_RO_generic 984 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 985 986 #define L2_S_PROT_U L2_S_PROT_U_generic 987 #define L2_S_PROT_W L2_S_PROT_W_generic 988 #define L2_S_PROT_RO L2_S_PROT_RO_generic 989 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 990 991 #define L2_L_PROT_U L2_L_PROT_U_generic 992 #define L2_L_PROT_W L2_L_PROT_W_generic 993 #define L2_L_PROT_RO L2_L_PROT_RO_generic 994 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 995 996 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 997 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 998 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 999 1000 #define L1_SS_PROTO L1_SS_PROTO_generic 1001 #define L1_S_PROTO L1_S_PROTO_generic 1002 #define L1_C_PROTO L1_C_PROTO_generic 1003 #define L2_S_PROTO L2_S_PROTO_generic 1004 1005 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1006 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1007 #elif ARM_MMU_V6N != 0 1008 #define L1_S_PROT_U L1_S_PROT_U_armv6 1009 #define L1_S_PROT_W L1_S_PROT_W_armv6 1010 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 1011 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 1012 1013 #define L2_S_PROT_U L2_S_PROT_U_armv6n 1014 #define L2_S_PROT_W L2_S_PROT_W_armv6n 1015 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 1016 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 1017 1018 #define L2_L_PROT_U L2_L_PROT_U_armv6n 1019 #define L2_L_PROT_W L2_L_PROT_W_armv6n 1020 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 1021 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 1022 1023 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6n 1024 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6n 1025 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 1026 1027 /* 1028 * These prototypes make writeable mappings, while the other MMU types 1029 * make read-only mappings. 1030 */ 1031 #define L1_SS_PROTO L1_SS_PROTO_armv6 1032 #define L1_S_PROTO L1_S_PROTO_armv6 1033 #define L1_C_PROTO L1_C_PROTO_armv6 1034 #define L2_S_PROTO L2_S_PROTO_armv6n 1035 1036 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1037 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1038 #elif ARM_MMU_V6C != 0 1039 #define L1_S_PROT_U L1_S_PROT_U_generic 1040 #define L1_S_PROT_W L1_S_PROT_W_generic 1041 #define L1_S_PROT_RO L1_S_PROT_RO_generic 1042 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 1043 1044 #define L2_S_PROT_U L2_S_PROT_U_generic 1045 #define L2_S_PROT_W L2_S_PROT_W_generic 1046 #define L2_S_PROT_RO L2_S_PROT_RO_generic 1047 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 1048 1049 #define L2_L_PROT_U L2_L_PROT_U_generic 1050 #define L2_L_PROT_W L2_L_PROT_W_generic 1051 #define L2_L_PROT_RO L2_L_PROT_RO_generic 1052 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 1053 1054 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 1055 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 1056 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 1057 1058 #define L1_SS_PROTO L1_SS_PROTO_armv6 1059 #define L1_S_PROTO L1_S_PROTO_generic 1060 #define L1_C_PROTO L1_C_PROTO_generic 1061 #define L2_S_PROTO L2_S_PROTO_generic 1062 1063 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1064 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1065 #elif ARM_MMU_XSCALE == 1 1066 #define L1_S_PROT_U L1_S_PROT_U_generic 1067 #define L1_S_PROT_W L1_S_PROT_W_generic 1068 #define L1_S_PROT_RO L1_S_PROT_RO_generic 1069 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 1070 1071 #define L2_S_PROT_U L2_S_PROT_U_xscale 1072 #define L2_S_PROT_W L2_S_PROT_W_xscale 1073 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 1074 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 1075 1076 #define L2_L_PROT_U L2_L_PROT_U_generic 1077 #define L2_L_PROT_W L2_L_PROT_W_generic 1078 #define L2_L_PROT_RO L2_L_PROT_RO_generic 1079 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 1080 1081 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 1082 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 1083 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 1084 1085 #define L1_SS_PROTO L1_SS_PROTO_xscale 1086 #define L1_S_PROTO L1_S_PROTO_xscale 1087 #define L1_C_PROTO L1_C_PROTO_xscale 1088 #define L2_S_PROTO L2_S_PROTO_xscale 1089 1090 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 1091 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 1092 #elif ARM_MMU_V7 == 1 1093 #define L1_S_PROT_U L1_S_PROT_U_armv7 1094 #define L1_S_PROT_W L1_S_PROT_W_armv7 1095 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 1096 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 1097 1098 #define L2_S_PROT_U L2_S_PROT_U_armv7 1099 #define L2_S_PROT_W L2_S_PROT_W_armv7 1100 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 1101 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 1102 1103 #define L2_L_PROT_U L2_L_PROT_U_armv7 1104 #define L2_L_PROT_W L2_L_PROT_W_armv7 1105 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 1106 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 1107 1108 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 1109 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 1110 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 1111 1112 /* 1113 * These prototypes make writeable mappings, while the other MMU types 1114 * make read-only mappings. 1115 */ 1116 #define L1_SS_PROTO L1_SS_PROTO_armv7 1117 #define L1_S_PROTO L1_S_PROTO_armv7 1118 #define L1_C_PROTO L1_C_PROTO_armv7 1119 #define L2_S_PROTO L2_S_PROTO_armv7 1120 1121 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1122 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1123 #endif /* ARM_NMMUS > 1 */ 1124 1125 /* 1126 * Macros to set and query the write permission on page descriptors. 1127 */ 1128 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 1129 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 1130 1131 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 1132 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 1133 1134 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 1135 (L2_S_PROT_RO == 0 || \ 1136 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 1137 1138 /* 1139 * These macros return various bits based on kernel/user and protection. 1140 * Note that the compiler will usually fold these at compile time. 1141 */ 1142 1143 #define L1_S_PROT(ku, pr) ( \ 1144 (((ku) == PTE_USER) ? \ 1145 L1_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0) \ 1146 : \ 1147 (((L1_S_PROT_RO && \ 1148 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1149 L1_S_PROT_RO : L1_S_PROT_W))) \ 1150 ) 1151 1152 #define L2_L_PROT(ku, pr) ( \ 1153 (((ku) == PTE_USER) ? \ 1154 L2_L_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0) \ 1155 : \ 1156 (((L2_L_PROT_RO && \ 1157 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1158 L2_L_PROT_RO : L2_L_PROT_W))) \ 1159 ) 1160 1161 #define L2_S_PROT(ku, pr) ( \ 1162 (((ku) == PTE_USER) ? \ 1163 L2_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0) \ 1164 : \ 1165 (((L2_S_PROT_RO && \ 1166 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1167 L2_S_PROT_RO : L2_S_PROT_W))) \ 1168 ) 1169 1170 /* 1171 * Macros to test if a mapping is mappable with an L1 SuperSection, 1172 * L1 Section, or an L2 Large Page mapping. 1173 */ 1174 #define L1_SS_MAPPABLE_P(va, pa, size) \ 1175 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 1176 1177 #define L1_S_MAPPABLE_P(va, pa, size) \ 1178 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 1179 1180 #define L2_L_MAPPABLE_P(va, pa, size) \ 1181 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 1182 1183 #define PMAP_MAPSIZE1 L2_L_SIZE 1184 #define PMAP_MAPSIZE2 L1_S_SIZE 1185 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 1186 #define PMAP_MAPSIZE3 L1_SS_SIZE 1187 #endif 1188 1189 #ifndef _LOCORE 1190 /* 1191 * Hooks for the pool allocator. 1192 */ 1193 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 1194 extern paddr_t physical_start, physical_end; 1195 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1196 struct vm_page *arm_pmap_alloc_poolpage(int); 1197 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 1198 #endif 1199 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 1200 vaddr_t pmap_map_poolpage(paddr_t); 1201 paddr_t pmap_unmap_poolpage(vaddr_t); 1202 #define PMAP_MAP_POOLPAGE(pa) pmap_map_poolpage(pa) 1203 #define PMAP_UNMAP_POOLPAGE(va) pmap_unmap_poolpage(va) 1204 #endif 1205 1206 #define __HAVE_PMAP_PV_TRACK 1 1207 1208 void pmap_pv_protect(paddr_t, vm_prot_t); 1209 1210 struct pmap_page { 1211 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 1212 int pvh_attrs; /* page attributes */ 1213 u_int uro_mappings; 1214 u_int urw_mappings; 1215 union { 1216 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 1217 u_int i_mappings; 1218 } k_u; 1219 }; 1220 1221 /* 1222 * pmap-specific data store in the vm_page structure. 1223 */ 1224 #define __HAVE_VM_PAGE_MD 1225 struct vm_page_md { 1226 struct pmap_page pp; 1227 #define pvh_list pp.pvh_list 1228 #define pvh_attrs pp.pvh_attrs 1229 #define uro_mappings pp.uro_mappings 1230 #define urw_mappings pp.urw_mappings 1231 #define kro_mappings pp.k_u.s_mappings[0] 1232 #define krw_mappings pp.k_u.s_mappings[1] 1233 #define k_mappings pp.k_u.i_mappings 1234 }; 1235 1236 #define PMAP_PAGE_TO_MD(ppage) container_of((ppage), struct vm_page_md, pp) 1237 1238 /* 1239 * Set the default color of each page. 1240 */ 1241 #if ARM_MMU_V6 > 0 1242 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1243 (pg)->mdpage.pvh_attrs = VM_PAGE_TO_PHYS(pg) & arm_cache_prefer_mask 1244 #else 1245 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1246 (pg)->mdpage.pvh_attrs = 0 1247 #endif 1248 1249 #define VM_MDPAGE_INIT(pg) \ 1250 do { \ 1251 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 1252 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 1253 (pg)->mdpage.uro_mappings = 0; \ 1254 (pg)->mdpage.urw_mappings = 0; \ 1255 (pg)->mdpage.k_mappings = 0; \ 1256 } while (/*CONSTCOND*/0) 1257 1258 #ifndef __BSD_PTENTRY_T__ 1259 #define __BSD_PTENTRY_T__ 1260 typedef uint32_t pt_entry_t; 1261 #define PRIxPTE PRIx32 1262 #endif 1263 1264 #endif /* !_LOCORE */ 1265 1266 #endif /* _KERNEL */ 1267 1268 #endif /* _ARM32_PMAP_H_ */ 1269
Indexes created Wed Jul 08 00:27:11 UTC 2026